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Euthanasia oregon

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Oregon s Death with Dignity Act--2013 - Oregon gov

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Why Oregon Patients Request Assisted Death: Family Members Views

assertion essay Follow the steps below to formulate a thesis statement. All cells must contain text. 2. State your opinion/main idea about this topic. This will form the heart of your thesis. An effective statement will. express one major idea. name the topic and euthanasia oregon assert something specific about it. be a more specific statement than the dahmer topic statement above. take a stance on an issue about which reasonable people might disagree. state your position on or opinion about the issue. 3. Give the strongest reason or assertion that supports your opinion/main idea.

4. Give another strong reason or assertion that supports your opinion/main idea. 5. Give one more strong reason or assertion that supports your opinion/main idea. 6. Oregon? Include an opposing viewpoint to your opinion/main idea, if applicable. This should be an argument for the opposing view that you admit has some merit, even if you do not agree with the overall viewpoint. Of Macbeth? 7. Provide a possible title for your essay. Thesis Statement Model #35;1: Sample Thesis Statement. Parents should regulate the amount of television their children watch. Thesis Statement Model #35;2: Thesis with Concession. Notice that this model makes a concession by oregon addressing an argument from the opposing viewpoint first, and then uses the Othello, by William Essay phrase even though and states the writer#39;s opinion/main idea as a rebuttal. Even though television can be educational, parents should regulate the amount of television their children watch.

Thesis Statement Model #35;3: Thesis with Reasons. Here, the use of because reveals the reasons behind the writer's opinion/main idea. Oregon? parents should regulate the amount of television their children watch because it shortens children#39;s attention spans, it inhibits social interaction, and it isn#39;t always intellectually stimulating. Thesis Statement Model #35;4: Thesis with Concession and Reasons. This model both makes a concession to opposing viewpoint and states the reasons/arguments for the writer#39;s main idea. While television can be educational , parents should regulate the amount of television their children watch because it inhibits social interaction, shortens children#39;s attention spans, and isn#39;t always intellectually stimulating.

Remember: These thesis statements are generated based on the answers provided on the form. Use the Thesis Statement Guide as many times as you like. Your ideas and the results are anonymous and by William Essay confidential. When you build a thesis statement that works for you, ensure that it addresses the assignment. Finally, you may have to rewrite the thesis statement so that the oregon spelling, grammar, and punctuation are correct. Thesis Statement Guide: Sample Outline. Use the outline below, which is alive based on the fiveparagraph essay model, when drafting a plan for your own essay. This is meant as a guide only, so we encourage you to revise it in a way that works best for you.

Start your introduction with an interesting hook to euthanasia oregon reel your reader in. Othello, Shakespeare? An introduction can begin with a rhetorical question, a quotation, an anecdote, a concession, an interesting fact, or a question that will be answered in euthanasia oregon your paper. The idea is to begin broadly and gradually bring the reader closer to the main idea of the paper. At the end of the introduction, you will present your thesis statement. Othello,? The thesis statement model used in this example is a thesis with reasons. Euthanasia Oregon? Even though television can be educational , parents should regulate the amount of television their children watch because it shortens children's attention spans, it inhibits social interaction, and dahmer it is oregon not always intellectually stimulating. First, parents should regulate the amount of television their children watch because it shortens children's attention spans . Notice that this Assertion is the first reason presented in the thesis statement. Remember that the thesis statement is curtain significance a kind of mapping tool that helps you organize your ideas, and it helps your reader follow your argument. Euthanasia Oregon? In this body paragraph, after the Assertion, include any evidencea quotation, statistic, datathat supports this first point. Explain what the evidence means.

Show the reader how this entire paragraph connects back to the thesis statement. Additionally, it inhibits social interaction . The first sentence of the second body paragraph should reflect an even stronger Assertion to support the watsons theory thesis statement. Generally, the second point listed in the thesis statement should be developed here. Like with the euthanasia oregon previous paragraph, include any evidencea quotation, statistic, datathat supports this point after the Assertion. Explain what the evidence means. Othello, By William Shakespeare? Show the reader how this entire paragraph connects back to the thesis statement. Finally, the most important reason parents should regulate the amount of television their children watch is it is oregon not always intellectually stimulating . Your strongest point should be revealed in the final body paragraph. Also, if it#39;s appropriate, you can address and refute any opposing viewpoints to iron significance your thesis statement here.

As always, include evidencea quotation, statistic, datathat supports your strongest point. Explain what the evidence means. Show the reader how this entire paragraph connects back to the thesis statement. Indeed, while television can be educational, parents should regulate the amount of oregon television their children watch . Significance? Rephrase your thesis statement in oregon the first sentence of the conclusion. Michelangelo's Fresco Essay? Instead of summarizing the points you just made, synthesize them. Show the euthanasia reader how everything fits together.

While you don#39;t want to Shakespeare Essay present new material here, you can echo the introduction, ask the reader questions, look to the future, or challenge your reader. Euthanasia? Remember: This outline is based on the fiveparagraph model. Expand or condense it according to your particular assignment or the size of your opinion/main idea. Again, use the Thesis Statement Guide as many times as you like, until you reach a thesis statement and outline that works for euthanasia, you.

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Oregon s Death with Dignity Law and Euthanasia in the Netherlands

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Oregon s Death with Dignity Law and Euthanasia in the Netherlands

How to euthanasia Write an Exceptional New-Grad Nursing Resume. Writing a new-grad nursing resume is a daunting task for most new-grads. The fear of having no experience and being unqualified leaves many wondering what details to include. Othello, Shakespeare? Moreover, many new-grads wonder how to structure their nursing resume in a way that best conveys their current skill-set and oregon, value to Othello, by William Shakespeare Essay prospective employers. As former recruiters, we reviewed thousands of euthanasia oregon, new-grad resumes. In this blog post, weíll draw on that experience to provide a comprehensive guide to creating an amazing nursing resume for new-grads. How to oregon Structure Your New-Grad Nursing Resume.

How you structure your resume has an impact on its effectiveness. Summary Of Macbeth? Letís first consider which headings to oregon include on your resume. There are certain headings that every new-grad should include and other headings that will depend on whether or not you have any applicable details to Othello, by William Essay include under those headings. Headings that every new-grad nursing resume should include (Required) Every new-grad resume should include the following headings (weíll discuss why we recommend these headings and euthanasia oregon, provide tips for each below): Summary Licenses and Certifications Education Clinical Rotations. Optional headings for your new-grad nursing resume. Each of the following headings should be considered and included based on whether or not you have relevant details to include:

Work History Affiliations Volunteer Activities Honors and Awards Skills Summary Languages. Now letís take a look at the ordering of the headings. Of course, your contact information should be at theory of caring, the top of euthanasia oregon, your resume. As usual, you should place the Summary as first heading on curtain your resume. Next, include your Licenses and Certifications if you have already obtained them. However, if you have not already obtained them, then you may want to push this heading farther down the list under your Clinical Rotations. Next, include your Education followed by watsons theory, your Clinical Rotations. You will undoubtedly find many who recommend that you place your Work History first.

Moreover, placing Work History before Education is the conventional standard. Oregon? As a result, itís difficult for some to trust advice that recommends placing Education first. So, hereís our supporting argumentÖ As a new-grad, you may not even have work experience. Iron Significance? If you do, itís most likely that you donít have applicable work experience and even if you do have applicable experience, itís most certainly not Registered Nursing work experience. You canít obtain RN work experience without an RN license and you canít get an RN license without first graduating from an accredited nursing program and passing the NCLEX. Moreover, your new-grad nursing resume should quickly convey that you are a new-grad. There is no point in by William Shakespeare, trying to hide this fact. If employers are considering new-grads for an open position, then recruiters and oregon, hiring managers are going to be receptive to your situation.

If theyíre not considering new-grads for the opening and are instead requiring experience for the position, then theyíre not going to be receptive to your situation. Othello, Shakespeare? Youíre not going to euthanasia trick them by putting your CNA or EMT work experience ahead of your education. In fact, doing this could make your resume even less effective as reviewers receptive to new-grads may never even get to your new-grad status before passing on the resume. Perhaps more importantly, our recommendation is significance based on what was desired by oregon, the hiring managers we worked with. Jackie Essay? You will find corroboration for this recommendation from reputable sources all over the internet. For example, the sample new-grad resumes from California State University Chico and University of Texas San Antonio both have the headings listed in the order we recommend. Euthanasia? Additionally, UC Davis Medical Center requires Education, Senior Preceptorship and Clinical Rotations on the resumes of all applicants to their nursing residency program. For further proof, letís take a look at what a hiring manager had to say about new-grad resumes.

As the Director of Workforce Development for Orange County Memorial Care University and a Board Member of the Association of California Nurse Leaders, Maria-Jean Caterinicchio, RN, MS said, ďIt (your resume) should state where you have done your clinicals and any certifications such as EKG and Shakespeare, ACLS. You can also include any conferences you have attended beyond the classroom.Ē Your Clinical Rotations and Education are key components of your new-grad resume! That takes care of the 4 required headings. Euthanasia Oregon? The 6 optional headings can be ranked as you see fit. Remember, you should only include these headings if you have substantial details to convey. And you may want to rank them in order of strength as they relate to the job in question. For example, if you have experience working as a CNA in a hospital setting, then your Work History should be given a higher ranking because it highly relates to the job youíre applying for.

Specific Details to Include on Your New-grad Nursing Resume. Youíll undoubtedly come across many people who recommend that new-grads use an Objective instead of Othello, by William Shakespeare, a Summary on euthanasia oregon their resumes. The argument is that you really have nothing to summarize as a new-grad. Of Caring? However, we think that Objectives are an outdated resume heading that do nothing to oregon advance your main objective of conveying why youíre the right person for the job. Michelangelo's Fresco Essay? Moreover, you can include an objective within a summary if youíre intent on euthanasia having one. Here are three articles from major publications that support summaries over Michelangelo's Fresco Essay objectives: Now, you may have heard that recruiters spend 6 seconds reviewing your resume. While we doubt that they really spend that little time reviewing each resume, we certainly believe that the time they spend is very limited. Therefore, your goal is to make sure your resume can be easily scanned, starting with your Summary.

You do not want recruiters getting stuck on your Summary by writing a big paragraph. Instead, use bullet points and try to keep each point at 1 to 2 lines . As for what to iron curtain include in euthanasia, your SummaryÖItís a good idea to iron curtain significance state that youíre a new-grad. You might summarize your clinical rotations. You may point out any special skills that you have, like second languages or computer skills. And, as mentioned previously, you may include an objective.

We recommend listing each license and certification with the following information: Full name of the license or certification. Full name of the issuing body of the license or certification. Expiration date of the license or certification if applicable. License or certification number if applicable. If your license is part of the Nursing Licensure Compact, then it should be indicated. Many nurses express privacy concerns over including their license numbers. Your nursing license number is made public through the state licensing board. It can easily be obtained using the basic information you provide on your resume. Euthanasia Oregon? Adding it simply assists those recruiters and hiring managers who need to look it up for verification as a result of hospital/employer policy. Education for Your New-Grad Nursing Resume.

You should display all of your relevant college education. So if you attended 2 colleges to attain your degree, then you should include them both. Please do not include your high school education. Oregon? We recommend including the following information for each pertinent education institution you attended: Full official name of the education institution. Curtain? City and State Dates attended.

Degree achieved. Euthanasia? GPA if it was good. There are several other details in addition to these that you may want to include regarding your education. Weíve had many new-grads inform us that in their area, employers were interested in knowing their HESI or ATI scores. Summary Of Macbeth? We recommend checking with your Nurse Educators or your schoolís Career Guide to see what they recommend. You may also wish to include relevant coursework and corresponding grades if you got an A. However, keep this brief and relevant to the job youíre applying for. Finally, you may wish to include any honors and awards you achieved if you would rather not place these items under their own heading. Clinical Rotations on Your New-Grad Nursing Resume.

Clinical Rotations are an extremely important part of your new-grad nursing resume. As illustrated above, hiring managers indicate that they want to euthanasia oregon see these details. Major teaching universities require that they be included on Fresco The Last resumes submitted for their residency programs. We consider them the crux of your new-grad resume. At a minimum, you should include the following: Details to include about Othello, by William Shakespeare Essay your clinical rotations.

Type of experience (Clinical Rotation, Senior Preceptorship, other). Euthanasia Oregon? Start and end dates. Total number of robinson essay, hours worked. Name of the hospital or institution. City and State. Name of the unit/department (examples: Intensive Care Unit (ICU), Medical Surgical Unit (MS), Labor and Delivery Unit (LD)). One common mistake to avoid when listing the name of the unit is listing the hospital specific unit name. Is Jeffrey? For example, the hospital specific unit name might be 3-West, but nobody outside the hospital knows what that means.

Instead, list the type of unit it was as designated by euthanasia, the type of patients the unit took. In addition to the details above, we also recommend including the following information: Optional details to include about your clinical rotations. Facility type: Every facility has a technical designation. For example, most hospitals are ďAcute Care HospitalsĒ. Other designations include Long Term Care Facility, Long Term Acute Care Facility, Childrenís Hospital, etc. Listing the facility type lets the reader know without a doubt what the setting was. Number of jackie, beds in the facility. List the facilityís trauma designation if applicable. Euthanasia Oregon? If the facility was a teaching hospital, then include that information.

Number of beds on the unit you were assigned to. Trauma designation of the unit you were assigned to if applicable. Oregon? Age range of the patients the unit cared for if applicable. Nurse to patient ratio on the unit. Type of charting system used at dahmer, the facility and name of euthanasia oregon, any EMR/EHR you gained experience with. Curtain? The grade you received if it was an A. As you may have noticed, many of the details we recommend are technical details pertaining to the facility and unit. These details convey so much about the setting you were in and the experiences you were exposed to with very few words. So including them provides the reader with a ton of useful information. Additionally, it demonstrates that you understand how import these details are to any healthcare organization, otherwise, you wouldnít have listed them.

Additional options for highlighting your clinical rotations. Finally, you may also wish to include specific details about the experience you gained while engaged with your clinical rotations. For example, did you have any experiences that might make you a more attractive candidate to the prospective employer? Did you learn anything specific about compassion for patients, team work, the importance of , learning and growth as a new-grad RN? If you did, then try to offer the specifics to euthanasia oregon illustrate exactly what happened. You may also be able to relate your clinical rotation experience to specific goals or problems of the employer youíre applying to. For example, maybe your research on the prospective employer turns up the fact that theyíre seeking Magnet Status. If one of the facilities that you worked at during your rotations was seeking to achieve the same goal, then you may be able to find some way to relate your experience to watsons it.

Or, perhaps the prospective employer is trying to improve their HCAHPS score and one of the facilities you worked at just achieved success with a similar endeavor. Oregon? There are limitless possibilities with this option. The main idea is to try and relate your experience during clinical rotations to a real problem or goal faced by the prospective employer. At this point, weíve covered each of jackie essay, our recommended required headings. As you may have noticed, weíve offered tons of oregon, options.

So many that if you were to incorporate them all, then your resume would either be too crowded or too many pages. Still? However, many of the details we offer are simply for your consideration. Itís not required to include them all. Iron Significance? So pick and choose the ones that work best for you by euthanasia, researching the job in question and determining which details will be of most value to the prospective employer. Optional Details for Your New-grad Nursing Resume. As indicated above, each of the following headings are optional for your new-grad resume. Oregon? You should decide whether or not to use them based on whether or not you have applicable details to provide for them.

Letís take a brief look at each of them. If you have work history, which most college students these days do, then you should probably include some reference to watsons of caring it on oregon your resume. Try your best to convey how the experience relates to nursing. This will be a lot easier to do if the experience was healthcare related. If all else fails, offer concrete examples of how you excelled at time management, team work, compassion, service, collaboration, or communication. One important issue to consider regarding work history is stability.

Many college students work several jobs during their college career for any number of reasons. Too many short term stints may exhibit instability to Michelangelo's Fresco The Last Essay prospective employers who are about to euthanasia oregon devote a large amount of resources to you. Act 2? So you may want to explain short-term work stints or leave them off of your resume. You should definitely use the Affiliations heading if you are already a member of a professional organization related to nursing. For example, if youíre a member of the American Association of Critical Care Nurses, then prospective employers will want to know. Iron? You may also include relevant college organizations such as Sigma Theta Tau, or the Student Nurses Association.

Of course, if the only organizations you belong to are scholastic, then you may choose to include them under your Education heading to save space. When listing your affiliations, consider including the following details: Full name of the organization. Date joined. Euthanasia Oregon? Your designation within the organization. Any special duties. Organization conferences attended. Including Volunteer Activities is Othello, by William Essay a great way to demonstrate compassion.

You may have volunteered for charity or at euthanasia, a healthcare facility. Consider including the following details: Full name of the organization. Summary Of Macbeth? Dates of engagement. Euthanasia Oregon? Quantify the number of hours volunteered. Description of duties and euthanasia, results you achieved if applicable. Any awards or recognition you received. If you have received many honors and awards, then giving them a special place on your resume may be warranted.

The other option is to mix them in throughout your resume where applicable. ? Consider including the following details: Name or title of the award. Oregon? Date received. Organization received from. Michelangelo's Fresco The Last? Significance of the award, or reason it was received.

For most new-grads, a Skills Summary heading may not be warranted. Skills summaries are intended to convey proficiency with specific skills. Summary? As a new-grad, you most likely havenít achieved proficiency with any aspect of nursing. However, if you have experience in a healthcare setting, then you may indeed be proficient with relevant skills. For example, you may be certified in phlebotomy or Crisis Prevention.

In any case, if you havenít achieved proficiency, then you may be better served by euthanasia, listing skills as details under the heading that pertains to where the skills were practiced. Additionally, you might consider utilizing a Skills Checklist during your job search. Jackie Robinson Essay? In case youíre not familiar, Skills Checklists are documents that allow healthcare professionals to self-assess their skills pertaining to oregon a specific profession or specialty within a profession. They are commonly used by healthcare employers of all types to gauge their employeesí skill sets. BluePipes has over summary of macbeth act 2 100 comprehensive skills checklists that you can complete, save and download at euthanasia, your convenience. You can print them out and take them to job interviews in order to easily convey your level of expertise with hundreds of skills. Again, as a new-grad, itís not advised to utilize a checklist for a nursing specialty like Intensive Care Unit because you most likely wonít have the required expertise. Oregon? However, if you have experience as a CNA, Phlebotomist, or LPN, then you could use one of , those checklists as a way to oregon stand out from the crowd.

These checklists are free to curtain significance use on BluePipes. Euthanasia Oregon? So, join today to take advantage! A recent study by curtain, Wanted Analytics found that ďbilingualĒ was the second most common skill listed on nursing job postings in euthanasia oregon, the United States. If you speak multiple languages, then itís definitely recommended that you include them under their own special heading! What Hiring Managers and Job Postings are Looking for in New-Grad RNs.

Itís important to iron remember that experience, temperament, talents, and euthanasia, convictions vary from person to person. While all new-grads may share certain commonalities, they are all unique in their own ways. Shakespeare Essay? Similarly, itís fine for new-grad resumes to share certain commonalities, but each should be unique in itís own way. As youíve seen, we have strong opinions on the structure of your resume and we provide many recommendations on various details to oregon include. However, weíre not writing the resume for you. In fact, we strongly recommend against the boiler-plate phrases that have become so common as a result of online resume builders.

So, when it comes to the meat of your resume, let the words of hiring managers and job postings guide your efforts. In other words, find ways to relate your unique experiences to what hiring managers and job postings are looking for. And always strive to provide concrete examples as opposed to generalizations. Assuming that youíre applying for a job through a job posting (as opposed to networking for a job), you should do your best to optimize your resume for the Applicant Tracking System (ATS). Weíve covered how to do this in a previous blog post, so we wonít rehash it here. The bottom line is jackie essay that you want to naturally include the key buzzwords and phrases used in the job posting in your resume. This way, youíre ranked higher by the ATS. Of course, youíre probably wondering what hiring managers are looking for! Weíve provided some examples above, but below are some direct quotes we found from interviews posted online. These quotes validate what our own experience as recruiters taught us. ďKnowing that new nurses are very green in euthanasia, regards to their technical skills, we look to whether a nurse is really ready to step into the profession.

We are looking for those who are really interested in making life better for people who are suffering.Ē Kimberly Horton, MSN, RN, FNP, DHA, Vice President and Chief Nursing Officer at oregon, Mercy Hospital and watsons of caring, Mercy Southwest Hospital in euthanasia oregon, Bakersfield, California. ďWe expect our new nurse graduates to robinson essay have the basic fundamental nursing knowledge and we are also looking for compassion, a sense of teamwork, accountability and communication. We look for an attitude of collaboration and communication.Ē Maria-Jean Caterinicchio, RN, MS, Director of Workforce Development for Orange County Memorial Care University and Board Member of the Association of California Nurse Leaders (ACNL) Always side on patient safety first. Euthanasia? Be open to feedback. Use your resources, such as more experienced nurses, physicians and other members of your team.

This will also help you build a support system. Always ask questions when you are unsure or donít know something. Discuss your feelings and/or concerns with your unit leadership. Othello, By William? From the first day on the job, be a team player. Greg Kingsley, RN, New Grad Nurse Recruiter, Emory Healthcare. With all of this in mind, itís important to remember that there is no one correct way to create your resume.

We certainly hope this guide provides an idea of best practices as well as an idea of what you shouldnít do. Perhaps most importantly, itís important to remember that your resume is just one facet of your job search. Euthanasia Oregon? And while your resume is important, the single most important thing you can do to Shakespeare land that first job, or any job for that matter, is NETWORK! Estimates indicate 70% to 80% of all jobs are filled through networking. Euthanasia? And itís always best to operate with the ď80-20 ruleĒ in mind. In other words, make sure that youíre focusing on networking as your main job-search activity because itís most often the determining factor in success. Thatís why we created BluePipes in the first placeÖto give healthcare professionals a professional networking platform capable of providing unique career management tools designed to help them solve their unique career challenges. Join today, itís free and easy! 5 Things that New Grad RNs and Experienced RNs Should Know About the Job Market A New Grad RN recently shared their frustration with us. How to Write an Effective Nursing Resume Summary Writing an effective nursing resume summary is easier said than.

8 Things Every Nurse Ought to Know About Online Nursing Job Applications Applying online is the norm for nursing jobs. Fresco The Last Judgment? We provide. So my situation is a little different. Iíve been a Dental Assistant most of my life and decided to change careers. Oregon? I have now achieved my RN. But it took me a lot longer than a traditional ADN program is supposed to take. I had an ďissueĒ at the first school I started the nursing program at and ended up needing to find another school to euthanasia oregon complete the program.

Is this something I should include in is jeffrey dahmer, my resume (as I see it as a negative thing) or how do I incorporate it to oregon benefit my appearance? I donít want to leave out info that can hurt me but Iím wondering if the info can hurt me if included. I agree with Kyle. List out your clinicals. Add a targeted bullet point under each one that relates to the job you are applying for. Learn about is jeffrey ATS. Euthanasia? Read the job posting.

What words are on there most? What qualifications MUST you have? What qualifications do they PREFER? All the ones you have Ė write them down. Iron? Yes, use their words. Also read their mission and values. Look through their website.

Encorporate their values with yours. Euthanasia? A great place to of macbeth do this is in your cover letter. What do you recommend to someone like me whose 19 years old. Has no work experience, this is my first career.. Euthanasia Oregon? my resume would be completely blank pretty much. I know you said donít include high school education.. buts thatís pretty much the only thing Iíve ďaccomplishedĒ so far, I was an honor student, GPA 3.9, Received an award for academic excellence all 4 years, advanced diploma.

And currently my GPA is 3.5, I havenít graduated yet but will in OCT, 2016 with my associates degree in nursing. Iím applying to a new graduate residency program now, that will start in euthanasia oregon, February. Please HELP! #128577; how can I make my resume better? Thanks for the inquiry Glenda. Most of the applicants to new graduate residency programs have similar circumstances. To make your resume stand out, be sure to oregon include the details described above regarding your various experiences including clinical rotations and education. Theory? Youíre welcome to oregon include your high school education. However, chances are it will not be considered. Just remember that most candidates are going to be in the same boat, so making sure you provide all the details hospitals like to see (as described above) will help you stand out.

I hope this helps! Great article! Finally people are talking about New Graduate Registered Nurses and the job search!! The Struggle is VERY real for new, old, reentry, and , RNís seeking a new specialty! Especially in oversaturated markets like California. I invite anybody who is seeking a job to join our Facebook Group RNInterview Tools. All are invited to share what worked for them, post questions, and seek support from others who understand. Members are landing job offers all over and we could not be more thrilled.

I definitely shared this article and have shared others from euthanasia, Blue Pipes in the past. Thank you for assisting all of us Nurses in our quest. Glad to hear the article is useful and is jeffrey alive, thanks for sharing, Melissa! Help! I just graduated in , May 2016 and got hired as an RN in a hospital. Unfortunately, I resigned after a month as I felt so overwhelmed in the unit I was assigned to. Should I include that one month experience in my resume? Thanks for sharing, Aleli and sorry to hear about the difficulties. Euthanasia Oregon? This is a tough situation.

I believe most career consultants would recommend leaving the job off of your resume. This is because youíll most certainly be required to explain the short duration in any interview. Moreover, the duration was so short that many employers wouldnít even require an explanation for the gap in employment. That said, you may want to consider the instructions on job applications. Some hospitals have very stringent rules for entering work history on their applications. For example, they might require every employer for the past 7 years to be entered on Othello, Shakespeare the application regardless of duration and also require applicants to provide an explanation of any gaps in employment of greater than 1 month. There will be a signing statement in the application indicating you attest the information is accurate and , complete.

If they find out you left the job off the application, it could result in iron curtain significance, a rescinded job offer. Although the chances of this happening are slim. I hope this information helps! Nursing is my second career. I taught elementary school before this. Should I include my education for that? Also, should I include teaching school in my work history? I taught for eight years in the same school, so itís a good example that I can hold a job long term. Thanks! Congratulations on your new career, Priscilla.

Previous work history and education are both optional for your new-grad nursing resume. Alive? In your case, I highly recommend including them both as they are both excellent experiences to display. However, be sure to keep them brief in order to highlight your nursing skills. I hope this helps! Hello, I was wondering how do I include my phlebotomy certification on my resume if it doesnít have an expiration date? If you are formatting your own resume, you can simply add the license without expiration dates. Euthanasia Oregon? However, Iím wondering if youíre using BluePipes to format your resume? Please let me know if so. Thanks! Hi iím just wondering do you have an example resume with all the information you have listed here for preview? thank you! My apologies, but we donít have a sample.

Weíll work on iron significance creating though. Euthanasia? Thanks! How about information on building a new-grad RN Cover letter? When listing previous certifications and jackie, licenses, should you list the initial date of obtainment or expiration/ renewal date? Also, regarding Applicant Tracking System, what is the rule regarding parenthesis ()? I ask because in my certifications I have ACLS, PALS, and a bunch of other alphabet soup acronyms. Should I use (ACLS) after Advanced Cardiac Life Support? Good questions! There are no steadfast rules, but we recommend listing the expiration dates. On our resume builder, licenses are listed with both the acronym and name. For example: ACLS Ė Advanced Cardiac Life Support.

That said, most resume parsers are quite advanced these days, so they should be able to contextualize what is meant by ď(ACLS)Ē. Euthanasia Oregon? However, as illustrated above, itís not necessary to use the parentheses if you donít want to. I hope this helps! Help! I work in a long term care nursing facility as an RN for about a year and half now. Robinson Essay? This is my first nursing job and nursing is my second career. Oregon? What can you suggest in writing my resume? Are my clinical rotations still relevant? Thanks. There isnít a steadfast rule that applies to your question.

I think itís fair to say that most recruiters and is jeffrey, nursing career advisers would say that your clinical rotations shouldnít be added to your resume after a year and a half of working in an LYC facility. That said, you might still list it in an effort to oregon land a job in act 2, a new-grad training program.

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Why Oregon Patients Request Assisted Death: Family Members Views

pclos resume It's getting late and tomorrow you have a busy day. So you save your work and shut down your computer. Euthanasia Oregon! The following day, you power up your computer and your heart sinks when you see the message kernel panic Ö or grub error xx and your machine will not start. What to do?

Well the good news is that the fact that you got one of euthanasia those messages suggests that it is no more than a software problem, and you may just need to fix up a configuration file or re-install the boot loading program. This is not difficult to do, but it helps if you understand what you are trying to achieve. So first of all, we need a little background information. I'll try to keep this simple. When you apply power to a computer, the processor needs to be told what to do. The motherboard stores a list of drives that the computer can boot from, and oregon knows the order in which these should be tried, and so points the processor to the first drive on the list. The processor goes to the very beginning of the storage area of the drive to look for more information. This storage area is euthanasia oregon, divided up into summary of macbeth smaller areas, known as sectors, and the processor looks at oregon, the first sector on the drive, which is known as the iron curtain Master Boot Record or MBR. The first sector of any other partition is also reserved, and is known as the euthanasia boot sector. There isn't sufficient space in here to store all of the information the processor needs, so it shows the still processor where to find the code that will complete the rest of the boot loading process, so that the processor can continue to a full system boot. The boot loading program used by PCLinuxOS is called grub (GRand Unified Bootloader), and oregon the code stored in the MBR is known as 'grub stage1.' The final bit of Michelangelo's Fresco Essay code loaded into memory is 'grub stage2.'

Stage 2 starts the kernel and will set up a temporary file system in memory, which contains things like modules and drivers that the kernel may need to complete a successful system boot. It does this using a file system image known as the 'initial ram disk,' or initrd.img. Unfortunately, we have a problem here. On the one hand we have stage2, which knows where the kernel and initrd are stored on the file system, but stage1 knows nothing about file systems. Enter stage1_5.

There are several of these and each one is file system specific having names such as e2fs_stage1_5 and euthanasia oregon reiserfs_stage1_5. The stage1_5 code in these files is the summary bridge between the euthanasia oregon two, but needs to be able to be found by stage1. Fortunately, due to the way that partitions are laid out on a drive, there are always some free sectors after the first reserved sector, and this is where the euthanasia extra code goes. Stage1 knows to always look in euthanasia oregon, the second sector of its root partition, and after executing the code there, grub will be able to find things in the file system. When sufficient work has been done setting things up so that the Michelangelo's Judgment Essay kernel can manage physical files systems, control is euthanasia oregon, handed to the kernel.

That's roughly how things work in PCLinuxOS, but there is a whole lot more to the grub system than described here, and this is not the only way to boot the system. What follows is applicable to PCLinuxOS distributions and has always worked for curtain significance me, but may need some modification for other systems. Oregon! Ubuntu, and all Ubuntu-based versions, now uses grub2, so this will definitely not work there. From the above, we can see that grub needs to be told three things that it needs to boot your operating system: Where is the kernel Where is the initrd Which drive or partition holds grubs stage1_5 and stage2. This information is most commonly passed to grub in its configuration file, which in PCLinuxOS is /boot/grub/menu.lst. Some systems call this file grub.conf. Michelangelo's Fresco Judgment Essay! If the euthanasia information passed in this file is incorrect, then a missing kernel or initrd will give a grub error, and a wrongly defined root file system will cause the robinson essay kernel to panic. The information can also be supplied on the command line at boot time, although this requires a little more effort to master. To repair the system, you can boot from the Live CD that you used to install PCLinuxOS. This will get an operating system running in Shakespeare Essay, memory, and then you can repair any damaged files on your hard drive.

The first thing you need to know is the drive and partition on which PCLinuxOS is installed, and is jeffrey still grub can help here. Euthanasia Oregon! After booting from act 2, a Live CD, open up a terminal and get administrative powers by typing: You will be prompted for a password. This is the administrative or root password, and not your own user password. Please remember that now you have administration rights you should be extra careful about euthanasia what you enter on iron, the command line. You will get a message about euthanasia oregon probing, and then you will enter the grub command shell, where you can enter commands and even reinstall the resident part of grub:

At the new prompt, enter the following: You will get a list of partitions that contain the grub stage2 file. For most people this will be just one partition, but if you multi-boot several Linux systems, then they will all be represented. All the partitions will be listed as (hd0,0) or similar, as grub doesn't understand hda1 or sda1. Of Macbeth Act 2! It sees them only oregon as drives.

Grub counts starting at zero, not one. The first number is the drive number, and the second number the partition number. Jackie Robinson Essay! Type quit enter to leave grub. Now we know the drive and partition that our operating system is installed on, we can mount it and have a look around. I'm going to assume now that the partition is (hd0,0), the first partition on the first drive. In the terminal, still as root, type:

You will have to change sda to hda if your drive is oregon, IDE. If you don't know, try typing fdisk -l enter to get a list of recognized drives. The drive is now mounted at /a, and so the kernel and initrd should be in /a/boot. The name of the kernel and the initrd are quite long and complex, so there are usually easy to type links (shortcuts) to refer to them. The kernels name begins with vmlinuz and initrds name begins with initrd. To see them, type the following and make a note of the names.

The name that ends in an '@' is the link, and iron you can use this in your grub configuration file. I now have two links named vmlinuz and euthanasia oregon initrd.img. I also know that the root device is (hd0,0), but I find using labels makes life easier. So, typing tune2fs -L kde4 /dev/sda1 gives my partition a label of kde4. I label all of my partitions in this manner. If you prefer, you can use the summary graphical PCLinuxOS Control Center, by going to Local disks Manage disk partitions Expert Mode to label your partitions. Now I can try and fix up the menu.lst file. I'll use nano, a command line text editor that is really easy to use to edit the file, but you can use any text editor you like that can save a file as pure text with no formatting. Open the menu.lst file from your installed system:

The original file looks like this: It really isn't as complicated as it looks. Watsons Of Caring! The first four lines set up the menu, and each block of three lines is an euthanasia oregon, entry in the menu, known as a stanza. Curtain Significance! Each of the above stanzas contains only three lines, although the magazine typesetting will probably break these up. The formatting in the menu.lst file is important. The three lines begin with 'title', 'kernel' and 'initrd.' Each should be exactly one line long, even though the 'kernel' line often becomes a rather long line. There can be additional lines in euthanasia, the stanza, but these lines must each be on one line. I'm going to add a new stanza (menu item) at the beginning, i.e. between the line that reads 'default 0' and the one that reads 'title linux:' Make sure that you leave a blank line before, and after, each stanza or grub will not know where each stanza starts or ends.

After typing that in, hold down the Control key and press X, you will be prompted to save the file. Just say yes. That should be enough to get you booted, although you will want to pretty it up once you are satisfied. You could, in jackie, fact, have just those three lines in menu.lst. I didn't attempt to repair the file. Euthanasia! Rather, I wrote my own set of robinson instructions that I knew to be correct to the grub configuration file, menu.lst, and in euthanasia, that way, I am in control. I also left the original set of instructions for grub intact. Later, when I am sure that I have a bootable system, I can go back and edit the file, but I still have the original file contents. The four lines at the beginning of the menu.lst file perform the following functions. Timeout=10 sets the length of time in seconds that grub will wait before booting the default menu item or, if none is defined, the first menu item. Pressing any key before that time cancels the countdown.

color white/blue yellow/blue sets the colors for the text menu (which you can get to by pressing the escape key whilst at the graphical menu. Significance! There are times when you may need to do this). The first pair of numbers sets the oregon foreground/background colors for dahmer alive the bulk of the menu, and the second pair serve to highlight the selected line. gfxmenu (hd0,0)/boot/gfxmenu tells grub where to find the graphical menu. default 0 sets the default menu item to boot, counting from 0. To improve on the simple 'no frills' stanza we can start adding things to the 'kernel' line. Adding splash=silent vga=788 at the end of euthanasia this line will allow the installed plymouth graphics theme to hide the scrolling text. The number 788 is optimal for most users' displays. If you intend to use hibernation to shut down your machine, you will have to tell grub where to find the data to resume the session.

This is euthanasia oregon, stored on your swap partition, and for that reason, this partition should be slightly larger than the installed memory if hibernation is to succeed. Michelangelo's Fresco Judgment Essay! If your swap partition is /dev/sdb1, then add resume=/dev/sdb1 to the kernel line. We can specify the partition in this manner, as grub will understand file systems and drive notation by the time it gets here. A default installation of PCLinuxos supplies three stanzas. The first one will provide a full graphical boot to the login screen. Euthanasia! The next one is named 'linux-nonfb,' or similar, and is jeffrey still alive allows booting without a graphical boot splash, which allows you to see system messges as the system boots. This is useful for troubleshooting. You can pause the oregon scrolling text with the Scroll Lock key on your keyboard. Curtain! The last one, named 'failsafe,' will boot to a limited shell in single user mode, where you can perform some administrative tasks, such as file system checks and dahmer alive root password recovery. When all is euthanasia, well, typing init 5 should get you back up to the login screen.

These three modes are accomplished by adding one of the following to the 'kernel' line, between the kernel and root partition declarations. When you know that your new menu item(s) boot the system successfully, you can delete the old ones, but make a backup of the file somewhere you can always get to it. If you precede each line with a '#' then that item will not appear on the menu. Essay! Any line starting with a '#' is treated as a comment, and is not executed. If the euthanasia grub set up itself has become corrupted, then it is a relatively easy task to reset it.

As before, open a terminal, use the command su to get root privileges, and start the Othello, by William Shakespeare grub command shell with the command. Use grub's find command to discover which partitions have grub's files on them. If there are more than one, then choose the partition where you have your repaired menu.lst file. Euthanasia! Tell grub about it by typing. Use the partition you chose here. Now tell root where to put its stage one file. Curtain! This is the drive that your motherboard BIOS will try to boot from. Note that no partition number is euthanasia oregon, required, as we are specifying a device.

That's it, we're done. Type quit enter to leave grub. If you want to be able to boot into one of several distributions, then this is is most easily achieved in this manner. At the end of the is jeffrey still alive installation process you are asked where you would like to install grub, and the default is the MBR of the drive you have installed to. Instead, select the installation partition . You will then be prompted for the drive to boot from. This is the same as the root - setup sequence we performed manually in grub at oregon, the terminal. You will now have two menu.lst files, one in the /boot/grub folder of the dahmer new installation and the original one. I am using /dev/sda5, which grub knows as (hd0,4), for a new installation of Zen-Mini. Oregon! Add the following lines to the original menu.lst. When I select this menu item, I will be taken to new screen showing the menu items and the graphics of the new installation. I can now have the menu.lst file in euthanasia, the new installation identical to my default menu.lst, with the only change being that every occurrence of (hd0,0) becomes (hd0,4), which makes system maintenance so much easier.

A stanza in the zen menu.lst might look like this: Here's part of my default menu.lst: I find this much easier to follow. To boot an operating system such as Windows, that doesn't use grub but has its own boot loader, you can proceed in a similar manner. You have to add a stanza to menu.lst like this: Note: Change (hd0,2) to the partition that windows is , installed on. rootnoverify works like the root command, informing grub of the oregon location of the next part of the boot code, but no attempt is made at jackie robinson, this stage to mount the partition, as this could be problematic for grub. makeactive sets this root partition active. chainloader +1 tells grub to look in the second sector of the partition for the boot code (the first sector is always reserved by the file system). Using the grub commands at boot time.

If booting fails, then it is still possible to get to a working system by using the jackie essay grub command shell. If you get the graphical menu, then pressing the escape key will drop to the text mode menu after displaying a confirmation dialog. It is possible that you have made a typing error in your configuation file, or that your editor broke a long line into two and grub can make no sense of it. From here, you can edit the line. Select the menu entry that doesn't boot with the arrow keys and press 'E' then enter. Pressing 'E' again will place the selected line in the grub shell, where it may be edited. The cursor will be at euthanasia, the end of the line, but you can move with the essay arrow keys, as well as the home and end keys.

Press Enter to accept any changes, or the summary escape key to return to the previous screen without saving. Press 'D' on a highlighted line to delete it which you may need to do if your editor has broken the line and you have a half line of euthanasia garbage. Press 'B' to attempt to boot with the modified lines. The changes exist only in memory and are not made to the menu.lst file. If this is the case, this should be modified when you get a successful boot. If you can find no errors in the lines, then all is watsons theory, not lost. Euthanasia Oregon! Press 'C' to get a command line, and this puts you in a similar same environment to that we used from euthanasia oregon, a terminal to reinstall the boot loader. will locate partitions on all installed drives which are candidates to become the grub root. Use the root command to point grub at that partition. To find the kernel on this partition, which should reside in the /boot directory, we can use grub's command completion feature. The kernel will be named vmlinuz Ö something.

Pressing the tab key here tells grub to fill in as much as it can and list all possibiltes. We know that vmlinuz is a link, so the other file must be the actual kernel, which we will use as the link may be broken. We don't have to type in the full name, just add the hyphen and theory of caring press tab to let grub fill in by William Shakespeare Essay, the rest. This also avoids typing errors. That seems to have worked so now we can do the same for the initrd. Ok! grub has all the information it needs so now we can try booting the system. All of the oregon above grub session was taken from an actual installation, so I know that it works. The safest way to try our some of these techniques is to practice on a virtual box installation. Oregon! It is easy to set one up, and there is an Othello, by William, excellent article on this in euthanasia, the October 2008 issue of the magazine written by parnote, the current editor.

The article installs windows, but the principles are the same for a PCLinuxOS installation.

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Why Oregon Patients Request Assisted Death: Family Members Views

a good lab report Iowa State University. Scientific research is a group activity. Individual scientists perform experiments to test hypotheses about biological phenomena. After experiments are completed and duplicated, researchers attempt to persuade others to euthanasia oregon accept or reject their hypotheses by iron presenting the euthanasia oregon, data and their interpretations. The lab report or the scientific paper is the vehicle of persuasion; when it is published, it is by William Shakespeare available to oregon other scientists for review.

If the results stand up to robinson essay criticism, they become part of the accepted body of scientific knowledge unless later disproved. In some cases, a report may not be persuasive in nature but instead is an archival record for future generations. For example, data on the distribution and frequency of rabid skunks in a certain year may be of use to future epidemiologists in deciding whether the incidence of rabies is increasing. Regardless of whether a report is persuasive or archival, the following guidelines apply. The purpose of an abstract is to allow the reader to judge whether it would serve his or her purposes to read the entire report.

A good abstract is is jeffrey dahmer a concise (100 to 200 words) summary of the purpose of the report, the data presented, and the author's major conclusions. The introduction defines the subject of the report. It must outline the scientific purpose(s) or objective(s) for the research performed and give the reader sufficient background to understand the rest of the report. Care should be taken to limit the oregon, background to whatever is pertinent to the experiment. A good introduction will answer several questions, including the following: Why was this study performed? Answers to this question may be derived from observations of nature or from the literature.

What knowledge already exists about this subject? The answer to this question must review the literature, showing the historical development of an idea and including the confirmations, conflicts, and gaps in existing knowledge. What is the specific purpose of the study? The specific hypotheses and experimental design pertinent to investigating the curtain, topic should be described. What materials were used? How were they used? Where and when was the euthanasia, work done? (This question is most important in field studies.) All figures and tables should have descriptive titles and should include a legend explaining any symbols, abbreviations, or special methods used. Figures and tables should be numbered separately and should be referred to in the text by number, for example: Figure 1 shows that the Michelangelo's Fresco The Last Judgment Essay, activity decreased after five minutes. The activity decreased after five minutes (fig. 1).

Figures and tables should be self-explanatory; that is, the reader should be able to understand them without referring to the text. All columns and rows in tables and axes in figures should be labeled. Oregon. See appendix B for graphing instructions. This section of your report should concentrate on general trends and differences and not on trivial details. Many authors organize and write the results section before the rest of the report. This section lists all articles or books cited in your report. It is not the same as a bibliography, which simply lists references regardless of whether they were cited in the paper. The listing should be alphabetized by the last names of the authors. Different journals require different formats for citing literature.

The format that includes the most information is given in the following examples: Fox, J.W. 1988. Nest-building behavior of the catbird, Dumetella carolinensis. Journal of Ecology 47: 113-17. Bird, W.Z. 1990. Ecological aspects of fox reproduction . Berlin: Guttenberg Press. For chapters in books: Smith, C.J. 1989.

Basal cell carcinomas. In Histological aspects of cancer , ed. Oregon. C.D. . Wilfred, pp. 278-91. Boston: Medical Press.

When citing references in the text, do not use footnotes; instead, refer to articles by the author's name and oregon, the date the Shakespeare Essay, paper was published. For example: Fox in 1988 investigated the hormones on the nest-building behavior of catbirds. Hormones are known to influence the nest-building behavior of catbirds (Fox, 1988). When citing papers that have two authors, both names must be listed. Euthanasia. When three or more authors are involved, the Latin et al. (et alia) meaning and others may be used. A paper by Smith, Lynch, Merrill, and Beam published in 1989 would be cited in the text as: Smith et al. Watsons Of Caring. (1989) have shown that. This short form is for text use only. Euthanasia. In the Literature Cited, all names would be listed, usually last name preceding initials.

There are a number of style manuals that provide detailed directions for writing scientific papers. Some are listed in further readings at the end of this section. All scientific names (genus and species) must be italicized. (Underlining indicates italics in a typed paper.) Use the metric system of measurements. Abbreviations of units are used without a following period. Be aware that the word data is oregon plural while datum is singular. This affects the choice of a correct verb. The word species is summary of macbeth act 2 used both as a singular and oregon, as a plural. Numbers should be written as numerals when they are greater than ten or when they are associated with measurements; for example, 6 mm or 2 g but two explanations of six factors. Summary. When one list includes numbers over and under ten, all numbers in the list may be expressed as numerals; for example, 17 sunfish, 13 bass, and by William Essay, 2 trout. Never start a sentence with numerals. Spell all numbers beginning sentences.

Be sure to divide paragraphs correctly and to use starting and ending sentences that indicate the purpose of the paragraph. Euthanasia. A report or a section of a report should not be one long paragraph. Every sentence must have a subject and a verb. Avoid using the first person, I or we, in writing. Keep your writing impersonal, in the third person. Instead of saying, We weighed the frogs and put them in a glass jar, write, The frogs were weighed and put in a glass jar. Avoid the use of slang and the overuse of contractions. Be consistent in the use of tense throughout a paragraph--do not switch between past and present. It is best to is jeffrey dahmer still alive use past tense. 10. Be sure that pronouns refer to antecedents.

For example, in the statement, Sometimes cecropia caterpillars are in cherry trees but they are hard to find, does they refer to caterpillars or trees? After writing a report, read it over, watching especially for lack of precision and for ambiguity. Each sentence should present a clear message. The following examples illustrate lack of precision: The sample was incubated in mixture A minus B plus C. Does the mixture lack both B and C or lack B and contain C? The title Protection against euthanasia oregon Carcinogenesis by iron curtain Antioxidants leaves the euthanasia, reader wondering whether antioxidants protect from or cause cancer. The only way to oregon prevent such errors is to read and think about what you write. Learn to reread and edit your work.

CBE Style Manual Committee. 1983. CBE style manual: A guide for authors, editors, and curtain significance, publishers in the biological sciences. 5th ed. Bethesda, Md.: Council of Biology Editors.

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fpga sample resume Seeking a challenging and rewarding contracts in ASIC/FPGA Design Verification. Overall experience of over 10 years in euthanasia oregon ASIC/FPGA Design/Verification Verified Fibre Channel - 1 and Fibre Channel Arbitration Loop RTL Developed TCP/IP Functional Models in SystemC and verified the TCP RTL implementation Designed and Verified ZBT SRAM and iron significance Flash interface for LEXRA RISC Processor Designed and Verified a Ingress FPGA [Virtex II] for Nortel s Gigabit Ethernet line card Verified SPI-4 Soft core and Synthesised the euthanasia same towards Virtex II FPGA Designed and Verified USB1.1 Serial Interface Engine SOC Integration of a Smart Card ASIC Participated in iron significance the development of a VHDL Simulator. Languages : VHDL / Verilog HDL, PERL, SystemC, Vera, C, C++ Simulators : NC Verilog, Verilog XL, ModelSim VHDL/Verilog simulators Synthesizers : Synopsys Design Compiler, FPGA Express, Leonardo Spectrum,Xilinx Implementation Tools, Synplicity Memory Compilers: Denali Pure View Foundry Tools : Samsung s Foundry tools Cubicware Protocols : TCP/IP, Gigabit Ethernet, Fibre Channel [FC - 1,FC - Arbitrated Loop], SPI-4, USB1.1, EP1284 and ISA. M.S. Electrical and Electronics Engineering. Created a detailed test-plan to verify the Fibre Channel [FC - 1 and FC - Arbitration Loop] RTL and verified the RTL as per the test plan Designed a Word Builder for the FC -1 block, integrated in the FC-1 RTL and verified the same. Verified the RTL implementation of TCP/IP Stack. A detailed test plan was created and euthanasia oregon SystemC models of the Essay functional blocks were written to test the whole of TCP/IP Implementation. Designed and verified the LEXRA RISC Processor Interface with the functional blocks and verified the euthanasia same. Designed and verified the ZBT SRAM and Flash interface for the Lexra RISC Processor.

Integrated all functional RTL modules and created a system level top. Perl scripts where written to manage the files and significance test cases. Created the Vera testbench environment for the whole chip. Modified the SPI-4 soft core both on the Sink and Source data paths. Synthesized the modified RTL code on Synplifypro and implement the euthanasia netlist on Xilinx Implementation tools targeting to Xilinx virtex II series. Verified the RTL and oregon post layout netlist for functionality and timing. Ingress FPGA for line card: Designed and implemented the Michelangelo's Fresco Network Processor interface on the Ingress traffic flow towards the Switch fabric. The module also implements policing, segmentation, Packet format modifications and sends the packets across to the switch fabric. Synthesizing the modified RTL code on Xilinx Implementation tools targeting to Xilinx virtex II series XC2V3000 . Gate count of the complete Ingress FPGA 1,800,000 gates.

Modified the Accelar Simulation Environment Nortel functional simulation environment used for iron significance, Verification used the same to verify the oregon modified RTL code and synthesized gate level netlist. The job involved understanding the Accelar simulation environment and modifying the The Last same in accordance with the oregon new requirement. Verified the synthesized code on the Modified Accelar regression simulation environment. Trojan ASIC - USB Smart Card Solution: Synthesized the DesignWare 8051 of Synopsys Inc towards Samsung 0.35u STD90 technology on Synopsys Design Compiler. Designed testbench to test the DesignWare 8051 functionality. Mapped to whole design to XILINX FPGA - virtex series - using the Exemplar s Leonardo spectrum and Xilinx M1 implementation tools. The pre-layout and post-layout simulations were done on MODELSIM simulation environment.

SOC integration of significance, Synopsys DW8051, Smart Card Interface chip, SIE USBC core. Project managed the whole simulation work of the oregon USB-Smart Card. Enhanced already present Smart Card Device Model. Responsible for testing debugging of the functionality of the of caring design. USB SIE Serial Interface Engine : Designed tested of all the modules of Serial Interface Engine. Project managed the whole simulation work of the Serial Interface Engine. Integrated the SIE with the USBC and Mapped the whole design to XILINX FPGA - 4000XL series - using the Exemplar s Leonardo spectrum and Xilinx M1 implementation tools. The pre-layout and post layout simulations were done on MODELSIM simulation environment. Euthanasia Oregon. Responsible for testing debugging of the functionality of the summary SIE USBC design.

Ultimate - VHDL simulator conforming to IEEE VHDL specification : Took part in the kernel development of the watsons of caring simulator. Design and implemented an euthanasia oregon, intermediate format for the simulator. Wrote extensive test cases to test the summary various constructs and expressions of VHDL according to SPEC defined by IEEE. References Furnished Upon Request. Development simulation/verification or design on high speed electronics. VHDL, C, MTI simulator, ModelSim, RiscWatch debugger. Digital Corp.

San Jose, CA. Hardware Development Engineer. Modified behavioral VHDL logic of an existing PowerPC 603 cpu simulation model to communicate between an ASIC and a C code simulator, including the addition of decoders, latches, and state-machine modifications. Designed VHDL logic code that enhanced the 603 cpu model by euthanasia generating an internal address bus busy signal when an address-only phase is initiated by the ASIC. Developed 200+ C testcases for functional simulation, system level stressing and debugging of the Othello, by William Essay ASIC s internal logic, including cpu and pci address space, SRAM, cache, BAR and other registers. Co-developed C code for oregon, parity generation on a PowerPC 603 address bus and euthanasia oregon the ASIC s read-only cache register contents. Developed test plans to verify functionality of the ASIC s internal cache, and its 603 bus logic. Board-level timing analysis and measurements of setup, hold, output valid times, overshoot, undershoot signal quality, frequency voltage margining for summary act 2, various end-of-life replacement chips on a Fiber-channel to PCI I/O adapter board used in high-end data storage servers. Simpson Communications Corp.

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Amtel Corp. Boxsboro, OR. Configured and validated the essay compatibility of various PCI and EISA LANs and SCSI controllers and devices on quad Pentium-Pro Servers. ADDITIONAL JOB EDUCATIONAL TRAINING: Fiber Channel, ATM VHDL course designing a 16-bit alu w/pipelined registers Analog RF/microwave theory, device physics theory, and CMOS VLSI design coursework COMPASS, SPICE, Touchstone/Libra, Fortran, Mentor, Viewlogic, FPGA Express and Synopsys tools. ME Electrical Engineering, University of Utah, Salt Lake City, UT. BS Electrical Engineering, University of euthanasia, Utah, Salt Lake City, UT.

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Extensive expertise in the Engineering Process. Highly skilled in Product Design Development of Electro-Mechanical Products. Participated in providing Technical Engineering Leadership and Support to System, Concept, Equipment, Readiness and watsons of caring Production Review in Transiting new Designs into a Solid Product. Developed and Documented Specifications, Concept Definitions, Analyses and Judgment Trade Studies of euthanasia, various Electro-Mechanical Systems. Highly Knowledgeable of CAD Systems in generation of Assembly Dwgs., Parts Lists, Detailed Dwgs.

Altered Item Dwgs. Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation, PWB Artwork, Mechanical Dwgs,as required. Extensive hands-on experience in System Debug Component Level Troubleshooting, Electro-Mech Assembly, Integration Test, with wire-wrap and soldering expertise. Othello, Shakespeare Essay. Integration and Test of a variety of Computer Hardware. PROFESSIONAL WORK EXPERIENCE. SMARTWORKERS WAREHOUSE, Inc. Fitchburg, MA. Assistant Store Manager/Customer Service Rep. Providing management assistance to Store Manager.

Responsible for opening and closing. Assignment of daily retail task and scheduling of available manpower. Oregon. Providing customers with benefits of my expertise in the Art of Woodworking. Upgraded and re-merchandise entire store increasing net sales by 30 . Have sold well over 250,000 woodworking tools in 8 months. MILLERVILLE PHOTO PROCESSING CAMERA, Inc. Iron. Millerville, MA. Photo Lab Technician/Customer Service Rep. Processing and developing all types of Photographic Media including Digital Photography. Handing of oregon, Customer questions and accountable for cash flow. Michelangelo's Fresco The Last Essay. Expertise acquired in the service and maintenance of Fuji Photo Processing Equipment. Generated documentation of all Photo Processing and Printing Procedures.

Adhered to EPA Hazard Waste Requirements. COMPUTER AIDED SYSTEMS Boston MA. Consultant Electrical Engineer/Electronic Technician. Provided WEB Based Engineering Design Services doing Schematic Capture and PWB Layouts of PLC Interfaces using OrCAD. Performed various Test Engineering activities. Involved in assessing and euthanasia performing the overall Functional and In-Circuit Test activities in The Last Judgment Essay the production and repair of the euthanasia oregon DC-40 Handheld 486 Datacomputer w/LCD Display, PCMCIA I/F, Irda I/F, Modem I/F , and associated Power Supply SMD Assembly. Performed evaluation and refinement of a variety of Functional Test operations, debug analyses and recommended solutions to improve the production through-put and provide fully tested hardware to the customers of contract manufacturing firms.

Created Final Test Procedure for the Nortel 1800 Chassis and Modules Communication System Card PC603 Based, Modem Assembly w/SMD Modem Daughter Cards. Documented and jackie robinson essay Performed Functional Test Procedure for TELCO Communication PWB Modules, WATERS Corporation PWB Module and a variety of MKS Sensor SMD Assemblies. ADVANCED SYSTEMS CO., Pillsbury MA. Senior Development Engineer 1992-1998. Electronic Design Laboratory Lead Engineer and Cost Account Manager.

Provided upper management monthly Progress Reports and Weekly Departmental updates. Interacted with all required government customer agencies, Program Management Office, Manufacturing Engineering and other Design Laboratories to meet corporate objectives and deadlines. Euthanasia Oregon. Managed and participated in Electrical Engineering involved in euthanasia the specifying, designing, development, testing, debugging and qualifying prototype Electronic H/W. Responsible for the daily technical operation and security functions of the DoD Closed Area Digital Laboratory Central Test Facility. Upgraded and maintained PATRIOT COMO Simulation Laboratory. Michelangelo's Fresco The Last Judgment Essay. Technical Integration Lead to an engineering group of 10 engineers, in both hardware and software. Incorporating, integrating and oregon testing PATRIOT COMO I/II Telecommunication Upgrades supporting electronic assembly upgrades through Manufacturing and Depot Integration.

Technical Lead Integration Test Engineer for the Radio Logic Routing Unit-Upgrade Integrated and of macbeth tested a number of VMEbus designed Modules i.e.SBC, SIO, EPROM, ethernet supporting the RLRU-U transition to production and on through qualification testing at Field Sites. Technical Lead Electrical Engineer for PATRIOT COMO UPGRADES participated and oregon provided input to System, Concept, Equipment, Readiness and Production Reviews. Assistant Subcontract Manager for is jeffrey alive, Smart Matrix Unit GTE and euthanasia oregon Lightweight Computer Unit SAIC integrated, tested and qualified into PATRIOT COMO. Development Engineer 1990-1992. Electronic Design Laboratory Lead Engineer and Cost Account Manager for TACIT Rainbow Mission Computer TRMC . Euthanasia Oregon. The TRMC is based upon a MC68030 with dual MC68332s along with two subsystems interface modules and a power supply.

Supervised and directed four Electrical Designers. Participated and provided Technical Engineering Support to System, Concept, Equipment, Readiness and Othello, Production Reviews transiting the oregon TRMC Design into a solid Product with the help of Concurrent Manufacturing Engineering. Developed requirement Specifications, Concept definitions, analyses and performance trade-offs of various system architectures. Generated Assembly Dwgs., Parts List, Detail Dwgs., Altered Item Dwgs., Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation,PWB Artwork, PWB Mechanical Dwgs. as required. Built, Serviced and Maintained the TACIT RAINBOW Software Development Facility, integrated prototype H/W along, with SPARC Workstations, IBM-PCs and Silicon Graphics Workstations in jackie robinson the performance of software code development, system simulation and software performance evaluations. TRMC 80 Logic in Altera FPGAs No PWB Design Errors. Directed Multiple Laboratory and Manufacturing resources into developing a fully integrated, form-factored and of caring tested unit which was integrated into the TACIT RAINBOW Missile Prototype and Tested using LABVIEW. Senior Electrical Engineer 1987-1990. Digital Design Laboratory Lead Engineer and Cost Account Manager. Provided upper management monthly progress reports and weekly departmental updates.

Assigned design tasks and maintained cost and schedule. Lead Engineer for MIL-STD-1760 Missile Simulator Unit MSU 68020 based simulated aircraft stores interface for F15/F16/F18. Provided User Interface ports Monitor, Serial and Parallel Printer interfaces. Tested and qualified to MIL-STD-810C 12 units. Lead Engineer for Missile Integration Test Set MITS Integrated, incorporated and euthanasia tested Short Round Test Set into MITS H/W to provided Full-Up Missile Test. Michelangelo's Judgment. Lead Engineer for Dynamic Software Test Facility DSTF for software development designed, developed, integrated and tested a facility based upon five MC68020s, simulated internal missile interfaces via specialization circuitry and utilization of Personal Computers. Electrical Engineer 1986-1987. Module Design Engineer responsible for all components of the Module Design Process. Oregon. Coordinated and supplied technical design input, integration test and operational inputs for innovative subsystem development.

Redesigned the Digital Signal Processor and upgraded Missile H/W turning TTL Logic into Gate Array Logic using reverse engineering techniques. Iron Significance. Designed and Supported two Missile PWBs using MENTOR, one a Data Acquisition Module 25 Analog/75 Digital and the other a Aircraft HOW Interface Module 50 Analog as part of Low Cost Seeker Program HARM. Engineering Specialist 1985-1986 Specializing in Motorola Microprocessors incorporation, integration testing. Designer for Drop Test Seeker DTS Program Zilog Z8002 based Integrated Custom 10K Gate Arrays with Micro-Wire Technology using MENTOR and VHDL PWB Designer of Pre-Amplifier Module 100 Analog using PSPICE and MENTOR Proposal Engineer for US Navy Outer Air Battle Program. RADMEX Inc. Boston MA. Senior Electronic Design Engineer. Performed and euthanasia Specified the Electrical Design, Electronic Circuit Prototyping, PWB Layout, Product Documentation, H/W Development, Integration and Testing of a Computerized Newspaper Pagination System for a start-up company. Product Line developed and marketed was the Breeze Workstation , BitCaster Data Controller , BitPrinter Printer , BitSetter Typesetter and Michelangelo's Fresco The Last Judgment Essay BitPlater Laser Platemaker . Involved in all phases of electronic and product design, S/W H/W integration, test, production implementation, field service and marketing. Design/Developed a Raster Image Processor based upon oregon the AMD2903 Bit-slice processor form factored on a 12 x 12 multi-layer PWB using inverse euro-connectors.

Designed/Developed a Micro-Controller AM2910 with extensive memory, which produced a 96-bit microword form-factored on a 12 x 12 multi-layer PWB. Developed unique high-speed clock using PAL Logic. Used Future Net and Multi-wire prototyping. Designed/Developed a Dual Port Module on a two-sided PWB using light table, which allowed the still alive i ncorporation of a wide range of oregon, Off-the-Shelf Multibus I Modules. DAYNEON COMPANY, Bedford MA. Test Engineering Aide.

Worked in iron significance the Missile Integration and Test Department of the Missile Guidance Laboratory while attending NU. Assisted in the integration and oregon testing of the prototype AMRRAM Missile. Involved in the development of a Missile Readiness Test Set MRTS . Responsibilities included: Creation of overall MRTS System Level Diagrams; Generation of Schematics, Part List and Wire Lists; Assembly Drawings. Othello, Shakespeare Essay. Oversaw building of unit and performed engineering inspections;Performed initial testing and qualification testing. PANAMETRICS Inc., Waltham MA.

Design Engineering Aide. Under direction of Physicist and euthanasia oregon Electrical Engineers worked as a member of the is jeffrey alive Radiation Physics Laboratory while attending NU. Performed tasks in Prototyping, Development and Testing of various, Satellite Subsystem H/W for GOES Program. Held various jobs while attending college. Worked as Security Guards, Cashier at Store24, Retail Sales at Building 19 3/4, Bottling Production Line, Electro-Plating Operator, and Warehouse Laborer. Euthanasia Oregon. Had own summertime Painting and Landscape Business. 1981 NORTHEASTERN UNIVERSITY US-MA-BOSTON. Bachelor s Degree BS ENGINEERING TECHNOLOGY. 1976 Sylvania Technical School US-MA-Waltham. Certification COMPUTER ELECTRONICS.

1974 UNIVERSITY OF MASS US-MA AMHERST. Courses PSYCHOLOGY/CRIMINAL JUSTICE. ELECTRICAL ENGINEER/TECHNICIAN with extensive hands-on experience in SYSTEM DEBUG COMPONENT LEVEL TROUBLESHOOTING, ELECTRO-MECH ASSEMBLY, with WIRE-WRAP AND SOLDERING EXPERTISE. Expertise with Microprocessor/DSP/Embedded Designs AMD, Motorola, Intel, TI ;Analog Design, RF Design, High Speed Digital Circuit Design; FPGA/PAL Logic Xilinx, Altera, Actel ; VHDL; Multilayer PWBs and SMD Assembly, EMI Design Techniques, Backplane Design Multibus I/II, VMEBus, ISA, PCI Bus Serial I/F: RS423, RS232C, RS422, RS485 PARALLEL I/F; 1553B I/F, IEEE-488; LCD Displays,PCMCIA I/F, Irda I/F, Modem I/F, SCSI1/2/3 I/F; Ethernet, Fiber I/F; Optics, Integration of a variety of computer hardware; Familiarity with Test Equip./ATE. PROJECTS, WORD, EXCEL, POWERPOINT, MENTOR Schematic Capture/Logic Simulation, PSPICE, CLARIS DRAW, MENTOR PWB LAYOUT, OrCAD,WINDOWS w/LABVIEW, MATHLAB; Assembly C Programming. DIGITAL TECHNOLOGIES, San Jose, CA. Involved in dahmer still Ethernet/firewall product development for the OEM customer base. Designed the architecture for the current ASIC Ethernet hub/switch. This SOC included an oregon, ARM 7 processor, 5 MACs, a Triple DES core and 24K of Dual Port SSRAM using .25-micron technology. Headed the design team in the implementation of the chip.

VHDL was used for the design implementation. Designed the board level firewall product that uses this ASIC. Implemented a Triple DES core into an Actel FPGA that was used on the low-end firewall product line. Of Macbeth Act 2. Designed a three-channel Fast Ethernet firewall controller using an Intel ARM 9 processor and oregon an ITE PCI bridge. In charge of curtain, engineering development of board level designs for both product and OEM reference. Additional engineering responsibilities include: Wrote specifications for both chip and euthanasia oregon board level products. Wrote guidelines for PCB layout that encompasses component placement for jackie robinson, high-speed signals and FCC compliance testing. Euthanasia. Incorporated manufacturability into designs including ATE. Developed and maintained project schedules. Interfaced with the software department for BIOS and POS functionality.

MIRRENFAX IMAGE PRODUCTS, Sacramento, CA. December, 1997 to February, 1999. MANAGER OF ENGINEERING. Manager of the hardware engineering team. Involved in product planning for a new family of OEM image processing controllers. These controllers are installed in high-end scanners and allow Virtual Rescanning while automatically changing the image characteristics deskew, thresholding, intensity, cropping, etc. . Responsibilities include interfacing with scanner manufactures during product definition, scheduling of product development, resource management, project management, ASIC vendor selection and CAD tool evaluation and purchasing decisions. Involved with defining the next generation Image Processing ASIC. Responsibilities included defining functionality, project management, and vendor coordination. Also, designed the euthanasia oregon system architecture for a second ASIC that became the system intelligence.

This contained an embedded ARM7 processor, PCI interface, DRAM, etc. Led the design efforts on this second ASIC. Both ASICs were in summary the 1M to 1.5 M gate range and implemented in .25-micron technology. VHDL was used for the design implementation. Designed several controller boards that used these ASICs for different scanners. CMD TECHNOLOGY, Sacramento, CA. June, 1995 to December, 1997. MANAGER OF ENGINEERING. Managed the Raid Division engineering team.

Responsibilities included scheduling, budgeting and product development for both board and system level Raid products. Involved in oregon defining the jackie next generation architecture of Raid controllers that was comprised of a four ASIC chip set. Project Manager for a Digital Equipment Corp. specific Raid controller. This project was a joint effort between CMD and Digital with CMD designing the controller and Digital doing the mechanical packaging. Responsibilities included coordinating the hardware efforts between the two companies along with designing a FPGA that interfaces to Digital s EMU and Fault Bus. Designed the Raid controller board that was used by Digital.

Designed several other Raid controller boards that were used for the OEM market. Member of the Change Control Board CCB and the Advanced Products Group. Involved in implementing procedures between Document Control and Engineering. CORSER CORP., Costa Brava, CA. May, 1992 to June, 1995. Involved in the design of a DAT tape controller ASIC which interfaced to a SP1 format tape drive. This ASIC was implemented in .8-micron technology. Designed the next generation DAT tape controller ASIC. This chip was implemented in .6-micron technology and has approximately 80K gates. Designed the tape controller board that uses the euthanasia new ASIC along with a Data Compression/SCSI ASIC, V50 microprocessor, 1 MB of dahmer, DRAM buffering and FLASH EEPROM.

Joined the Arcuate Scan Tape group and designed an ASIC used in controlling the tape head preamps. This ASIC was mounted to the head assembly using chip-on-board technology. Also designed the Servo Gate detection ASIC used for head positioning. All ASICs designed and simulated at Conner were done using VHDL. IRVEL CORPORATION, Scottsdale, Arizona. December, 1988 to April, 1992. MANAGER OF ENGINEERING. Management responsibilities for engineering, software, and test departments.

Established procedures in top-down design methodology and functional specifications for the Software and Hardware Departments. Euthanasia Oregon. This provided a path for designs with a high degree of jackie essay, modularity and ease of euthanasia oregon, software/hardware integration. Defined future products and initial marketing strategies. Designed a proprietary Error Detection and Correction ASIC to be used in memory intensive products. A 16 and 32 bit version of this ASIC was designed in 1-micron technology and consisted of 34K gates. CAD tools used in these ASIC designs include Cadence for schematic capture and Verilog for simulation. Also designed a PC compatible memory board that incorporated this ASIC. Developed specifications, in conjunction with IBM Boca Raton, Florida , for a high performance PS/2 memory board. Involved in setting up incoming test procedures for partial memories using a Teradyne tester. Two patents emerged from the euthanasia oregon research of The Last Judgment, memory subsystems. FUTURAMA, Sacramento, CA.

October, 1984 to November, 1988. PROJECT MANAGER/SENIOR ENGINEER. Involved in writing product specifications for oregon, an advanced system architecture that was incorporated into a microprocessor development system. Interfaced with the software development group to identify areas of concern when porting UNIX on to the new system. Designed a 68000 based CPU board for this development system. During the design phase of the euthanasia oregon CPU, research was done on interfacing a 68000 to various memory management techniques along with different bus structures Multibus, IEEE 896, and euthanasia oregon VME . Designed the system protocol that provided an efficient means of communication between the CPU and intelligent, DMA driven, I/O controllers. Designed an intelligent SCSI controller that used this protocol. TRIANON CORPORATION, Sacramento, CA. March, 1981 to October, 1984.

PROJECT MANAGER/SENIOR ENGINEER. Project Manager for the Mark III minicomputer. Responsibilities included managing an engineering team and coordinating the software and act 2 manufacturing departments efforts on the project. Euthanasia Oregon. Designed the hardware and firmware for the Mark III Peripheral Interface Board that contained a tape streamer interface, four asynchronous ports and dahmer alive a two-port SMD/CMD disc drive interface. The Peripheral Interface Board was designed using discrete logic and incorporated the 2903 bit slice architecture for the micro-engine. The firmware consisted of 32 bit-wide microcode. COMPUTER AUTOMATION, Sacramento, CA. June, 1977 to March, 1981. Engineering team member involved in the development of oregon, a new processor and the related I/O controllers.

Designed the interface protocol and an I/O relay controller for Shakespeare, this processor. This team was located in oregon Dallas, Texas. Previously: Designed a debug module including hardware and of macbeth firmware that could be used for debugging Z80 software. There was also a 32-channel trace for storing address, control, and data lines upon receiving a pre or post trigger. The back-end contained the necessary handshaking to a modem so the board may be used remotely from the operator.

Initial assignments upon euthanasia oregon joining the company involved sustaining engineering hardware and firmware for robinson, a disc drive controller, synchronous communications controller, MOS memory board and static problems with CRT s. BSEE, California Polytechnic University, San Luis Obispo, California, 1977. Concentration in Computer Systems. Will be furnished on request. Six years of strong experience in research, analysis, design, development of instruments using VHDL/VERILOG, ASIC Design, FPGA design, digital design techniques, design using microprocessors and micro controllers. Expertise in of caring design and simulation of electronic circuit boards using orcad, spice, circuit maker and euthanasia smart work.

Expertize on Active HDL simulation package. Languages: C, C++ Application: FPGA, ASIC design, PCB design, Digital and analog circuit design Tools: Xilinx, Xilinx FPGAs xilinx 4000XL series, XILINX VIRTEX series , Cypress. Hardware Definition Language HDL : Verilog, VHDL, 8051 assembly HDL Tools: ModelSim VHDL, Leonardo Spectrum, RAD51 assembler, ORCAD, Spice. Compiler: AVC51 Operating System: Unix, Windows NT/95/98. Digital Automatic Moisture Computer. September 2001 - Till date.

Development of a stand alone device to measure moisture content of dahmer still alive, various agricultural products. Oregon. Involved in Design and development of automatic moisture meter both independent and computer interfacable. First prototype developed around 8051 microcontroller using AVC 51 for embedded system. Involved in sensor design. Robinson. Design and coded same using C. Handled design and fabrication of analog and digital boards for first prototype. Second prototype being developed as full custom SOC System on chip for the calibration circuit around microcontroller 8051using simulation and Othello, by William synthesis tools of mentor graphics. The input taken by sensor directly displayed in terms of percentage moisture. Development of calibration technique based on method of least squares. Writing source code and test benches in VHDL for interfacing of 64K RAM, ROM, decoder and their interfacing with the oregon A/D converter and PGA.

Simulation of calibration process and verification of functionality and jackie robinson essay timing errors for same. Synthesizing code on Xilinx virtex series using Xilinx FPGA. Environment: RAD51 assembler, AVC51, Mentor graphics, VHDL, Modelsim and Leonardo Spectrum, Xilinx, Virtex, Windows NT. Central Scientific Instruments Organization. 8 BIT Microcontroller ASIC Design Engineer. Involved in design of a 8-bit micro-controller having features of INTEL 8051 microcontroller. The FPGA consists of 128K RAM and 64k ROM and is jeffrey dahmer still alive is instruction compatible to the Intel 8051.Prepared library package for the instruction set of the microcontroller in VHDL. Wrote source code for the ALU to perform various arithemetic and logical opeartions. Oregon. Source code for the RAM and curtain significance ROM entity was written and debugged using test bench generation schemes. A complete model of the euthanasia oregon FPGA was designed using the above logical blocks and the design was implemented on Xilinx VIRTEX FPGA. Iron Curtain. a memory mapped output port was also added to the design. Environment: VHDL, Intel 8051 training kit, mentor graphics software , synopsys , Xilinx tools.

Central Scientific Instruments Organization. Microwave Oven ASIC Verification Engineer. Involved in the design of high frequency switching circuit to operate at 2.5 GHZ using spice simulation software.Involed in counter design for the programmable counter for the magnetron switching circuit. Involved in debugging, verification and euthanasia analysis of critical timing parameters for low power consumption and area size using Mentor graphics Leonardo spectrum synthesis tool . Synthesized circuit around rtl resistor transfer level after calculating timing delays and critical path parameters. Environment: Spice simulation software for Shakespeare Essay, mixed mode signals, Mentor graphics simualtion and synthesis tools. Department of Science and Technology DST. Video Chip simulation ASIC Verification engineer. A VMIS Video million images per second embedded processor was studied and was simulated for various digital applications. Captured top-level video inputs simulation of euthanasia, VMIS video million images per second TV controller chip having an embedded processor. Enabled signal processing for digital applications.

Worked in a team for , simulation of chip. Carried out chip verification using using tools from mentor graphics. Verified ASIC for rtl resistor transfer logic syntax and euthanasia semantics. Used Configuration Management Tool for database version control. Environment: Embedded processor from sigma Electronics, Mentor graphics tools, VHDL, Windows 98. Technology mission for oil seeds and pulses.

Sept 1998- June 1999. NIR Near Infra red BASED CEREAL / GRAIN ANALYSER Hardware engineer. Selected photodiodes according to wavelength of various samples to be measured for different parameters. The selection of photodiodes was done to opearte at radio frequencies. Designed analog and digital board around SPICE simulation software. Robinson Essay. Interfaced memory and display using embedded system programming using AVC 51, RAD 51 around microcontroller 8051.

Further, an FPGA was developed to perform the application of microcontroller 8051 and the entire calibration circuit was interfaced around the euthanasia Xilinx FPGA. Coded using VERILOG. The digital circuit associated with ROM, RAM, decoder,latch was implemented with the developed Xilinx FPGA microcontroller . As a team member wrote source code for the FPGA microcontroller features and tested the by William Essay functionality of interfacing circuit and simulated it using modelsim VERILOG. Environment: Microcontroller 8051, AVC51 and RAD51, Spice, Mentor graphics tools, model sim, Leonardo spectrum, Unix shell scripts. Department of Science and Technology DST. CPU Central Processing Unit Design ASIC Design Engineer.

Designed and developed a 8-bit microprocessor. The device consists of a RAM, ROM, a high speed ALU, shifting, decoding and oregon multiplexing circuitry. Made package for the instruction set of 8085 in VHDL. Othello, Essay. Wrote source code for the ALU to perform arithmetic and logical operations using VHDL, source code for the RAM and ROM implementation. Simulation of the functionality of the processor using test benches on Active HDL simulation package in oregon Window NT environment. synthesized the same on XILINX FPGA.

Environment: Active HDL, Vinytics 8085 microprocessor kit, Xiilinx spartan series,Windows NT. Technology Mission of Oil seeds and Pulses. Digital aflatoxin meter Test Engineer. Designed electronics related to system around ORCAD IV , checked for the functionality of the design using mixed mode signal simulation around ORCAD IV and development of calibration software around microprocessor 8085. Documented instrument for transfer of know how and providing intensive training to user on how to use same. Environment: ORCAD IV, Vinytics 8085 kit, assembly programming for 8085. Department of science and technology. Sept 1996- March 1997.

Gold Analyzers Test Engineer. Developed analog and watsons of caring digital electronics design circuit board using ORCAD. Euthanasia. Checked the functionality of the same and its interfacing with the sensor. Documentation of instrument. Involved in Fresco The Last Judgment Essay selection of principle of purity measure using non-destructive technique based on energy dispersive X-Ray fluorescence spectrometry.

Environment: ORCAD Version 1V, Windows 98. The projects around VHDL were coded and of caring tested before synthesis and also associated with PAL Programming, analog and breadboard testing. Responsible for integration and test of a UART, real time clock, keyboard controller, DMA controller and interrupt controller chip. This helped in gaining good understanding of ASIC design and verification methodologies along with PAL and FPGA programming. Responsible for working with clients on intensive short term methodology training. Responsible for training students in VHDL, synthesis and methodology. Aid in adaptation of training materials and development of new training classes. Iron Significance. Paper publications and presentations have been made on Digital Automatic Moisture Computer and Capacitive moisture measurement of grains and euthanasia oregon oil seedsin various national journals.

Training has been imparted to various engineers and students of engineering colleges from time to time. Significant contribution in The Last Judgment Essay organization of various seminars and conferences related to instruments developed, various projects for water quality monitoring and soil analysis have also been designed and developed. B.S. in Electronics Engineering. Assume a role in ASIC Verification/Applications/Design Engineering. 4+ years experience in the EDA Verification Industry. Senior Project Engineer (Promoted from Applications Engineer) Technical Lead for a TtME (Time to Market Engineering - a design verification consulting service) project for a Germany based company. Successful completion of the project lead to the sale of an emulation system.

Verified a 2+ million gate ASIC design. Assisted in Shakespeare project startup, Assessed project needs for verification and implemented design optimizations (for environment, RTL level and simulation). Executed project milestones such as running RTL design (Verilog and VHDL) through synthesis and simulation, providing training implementing Cadence verification tools on site. Used test benches for passing vectors and debugging simulation differences. Implemented Verification Flow. Identified introduced Cadence tools to the Verification process.

Advised on design methodology and validated the subsequent setup. Lead Engineer for a European account (Philips - HDTV division): Consulted on Verification flow, and provided optimization ideas. Offered on site support and tool integration. Implemented a synthesizable cycle based design and test bench, and helped with the execution. Assisted in customer evaluation (San Jose based IC design company for DTVs) for a simulation acceleration beta product. Worked with verification engineers to write optimized test benches. Worked on a product evaluation with Ericsson, Sweden, that resulted in sales for numerous simulation software licenses.

Worked closely with Quickturn RD and iron curtain significance a third party RD (Verisity) that provided the testbench generating tool. The customer desired a combined product of 3 verification products along with a testbench generating tool. Worked with QT and euthanasia Verisity s RD to integrate all of these products. Provided post-sales technical support and by William Shakespeare Essay worked to increase the simulation performance. Used profiling tools to determine simulation speed bottlenecks. Implemented RTL and C model design changes for maximum performance optimizations. Successfully completed a TtME project with Ericsson, Germany, over a four-month period. This involved remodeling (in Verilog) significant portions of watsons of caring, their design, testbench and memory models to be cycle based. Debugged differences in simulation results between Speedsim and the customer s internal simulator. Successfully completed a two-month TtME project with Cabletron.

Support included consulting on testbench methodologies, creating a synthesizable testbench, remodeling LSI memories to be cycle based, and making the LogicVision environment compatible to Speedsim. Assisted the Quickturn India Distributor with a customer evaluation. Responsibilities included going on site and oregon using test bench methods, passing vectors for showing proof of Speedsim functionality and performance on their design. Provided training to Application Engineers on topics related to simulation/acceleration tools during boot camps and other training sessions. Euthanasia Oregon. Worked on numerous customer benchmarks which required verifying 1+ million gate ASICs with Quickturn/Cadence lint checker, synthesis, simulation, acceleration and emulation tools.

Presented demos and presentations at euthanasia DAC 98 and DAC 00. Corporate Technical Support Specialist: Provided technical support for all of Quickturn s Simulation/Acceleration products. Clients included Ericsson, Intel, IBM, Lucent, AMD, Fujitsu, Philips and Mitsubishi. Played a product specialist role, with responsibilities including: Supporting Customers Quickturn Application Engineers: coordinating and resolving software, hardware and design related issues, problems, bugs and questions. . Providing workarounds to customer issues and working with RD to get critical customer bugs fixed as soon as possible. Was hired as ASD s (advanced simulation division of Quickturn) very first technical support specialist for Speedsim. ATRA Corp., Bayer Inc. Co-Op Internship (full time) Modeled a MC68HC11E9 Microcontoller Unit in VHDL.

The unit included microprocessor and euthanasia oregon memory components. Implemented design and verification with the help of summary of macbeth, ViewLogic tools like ViewDraw, ViewSim and euthanasia ViewTrace. M.S, Electrical Engineering, University of Massachusetts, Lowell, MA Dec 96. B.S., Electrical Engineering, Regional Engineering College (REC) Surat, India Aug 94. Expertise in dahmer Cadence Simulation, Acceleration and Synthesis Tools. Experienced with ViewLogic Schematic, Design and oregon Waveform Viewer tools. Simulation software: Powersuite, Speedsim, Megasim, PowersuiteVHDL, SPICE Emulation/Simulation Acceleration Cobalt, Radium, Palladium DAI: SignalScan, CompareScan Novas: Debussy Mentor Graphics: MTI View Logic: ViewDraw, ViewSim and ViewTrace. Strong Verilog skills, VHDL, C, Unix, Perl. References available on request. ASIC PHYSICAL DESIGN ENGINEER.

To achieve excellence, to be resourceful and oregon optimistic and to pursue a challenging career in VLSI design. Area of specialisation : ASIC Design Flow and Methodology, Simulation, Synthesis, Floor plan, Place Route, Timing Verification, CTS. Summary in watsons theory of caring short : Have got more than 20 months of experience in euthanasia oregon the field of VLSI. Worked in logical design for 8 months rest in physical design. Oregon. Moreover i have done my academic project in VLSI field. Arsanti!

Software Development Center(I) Pvt Ltd. Design Service Engineer(Physical design) Creating various test cases Benchmarks for customers. Watsons. Used to create testcases for QA of Avanti tools. Oregon. Creating testcases to check various releases of Avanti tools. Clearing Customers doubts queries regarding design tools. Vdesign Training development Centre Pvt lt. Trainee Design Engineer. Responsiblities : Logical design Digital design. Writing Verilog codes for various small Designs. Writing Test benches for designs.

Writing Scripts to check the designs. Undergone training on FPGA/ASIC design flow(logical design) and methodology,HDL coding for circuit implementation and test bench,simulation, timing Verification,Floorplanning,Place Rout (Vdesign Training Development Centre, PondyCherry). Undergone training on ASIC design flow(Physical design), Datapreparation, Floorplan,Place Route,timing, Physical Verification(DRC LVS). (Time To Market Ltd, Secunderabad). Projects carried out: (Physical Design) Design Specification: Hierarchical design with 5 softmacros. Hierarchial Floorplanning of of caring, Top Cell with core utilization of 75%, alongwith floorplanning of each soft macros with utilization of 80%. (Tool used Planet PL ApolloII) Timing Driven Placement of each soft macro with constraints from Synopsis Design Constraints(SDC). (Tool used ApolloII Saturn) Clock Tree Synthesis (CTS) of eachsoft macro with a target of skew of euthanasia, 0.2ns and phase delay 0f 2ns.

The CTS is , carried out for the Top Cell also. (Tool used ApolloII). Routing of each macro and the Top Cell. Euthanasia. (Tool used ApolloII). Physical Verification for DRC LVS for each macro and the Top Cell. (Tool used Hercules). Company : TTM( as a part of training program in Physical Design) Designing of Standard Cells of euthanasia, 0.24 technology along with DRC LVS check. (Tool used Enterprise Hercules) Die Reduction Power Analysis : With a core utilization of 98.5%. Contains 19 hard macros, and 28k standard cells. (Tool used ApolloII Mars-Rail) Timing driven :Flat design with an is jeffrey still alive, initial slack of -61.3, and congestion overflow of 4.03%. (Tool used ApolloII Saturn) BenchMark For LSI logic involving diesize with 30k std cells with core utilization of euthanasia oregon, 96%. BenchMark For LSI logic involving Congestion driven placement with a core size of 26,000,000 micro^2. Bench Mark for Teralogic involving timing with Tristate Nets High Fanout Nets with timing specs difficult to meet. Bench Mark for Teralogic involving Design Planning starting from synthesis to Global rout Its mearly an analysis. (Tools used for above BM's: Apollo, Saturn, MilkyWay, JupiterP)

EIGHT-BIT MICRO CONTROLLER. DESCRIPTION: The microcontroller which is the true computer on chip.The design incorporates all of the Michelangelo's The Last features found in a microprocessor ie. CPU,ALU,SP,PC,genaral purpose registers and special purpose registers.It also has added the oregon other features needed to make a complete computer ie.ROM, RAM, parallel port, serial port, counter and clk circuits Like microprocessor , microcontroller is a general purpose device but one that is meant to read data, perform limited calculation on that data and controls its environment based on these calculation. TEAM SIZE : 7 members. DURATION : 3 months. MY PARTS : CPU, counter timers, Interrupts, ROM and RAM. POLARIS for simulation. EXPLORERTL for RTL analysis. RTL MODEL OF FOUR BIT MICROPROCESSOR : DESCRIPTION: This four bit processor consists of the following components such as multiplexer, program counter,register,instruction decoder,ALU and timimg control,RAM and ROM .RTL code and testbench had been written for euthanasia, all the above units.Various stimuli had been given and jackie robinson essay the logic had been validated. TOOLS USED : simulator : MODEL SIM PE 5.3b.

DURATION : JAN-2000 to APR-2000. COMPANY : Vdesign, Pondycherry. 10th Matriculation 1993 -1994 74% Higher Secondary 1994 -1996 81% B E in euthanasia Electronics and Communication 1996 -2000 70% (Affiliated to Madurai Kamaraj University, TamilNadu). Hardware languages : Verilog. ASIC Methodologies : RTL and Behavioural. Assembly languages : Microcontroller. Software languages : C. Operating Systems : Unix,Windows. Script Language : Perl, Unix Shell Scripts, Scheme Scripts(Especially Avanti's Scheme), AWK, SED. Time Conscious. Othello,. A go-getter. Quest for euthanasia oregon, perfection in all assignments.

Date of Birth : 02-08-1977. Language Known : Tamil, English. Nationality : Indian. Marital Status : Single. References : will be provided on request. Three years of strong experience in VLSI/ASIC/FPGA design using Verilog HDL, VHDL, VERA HVL, VI editor, VIM, ModelSim, Xilinx FPGA Foundation series, Turbo C, SignalScan, Advanced Norton Editor, Synopsis DC, Cadence Artist, SPICE, SimG, ADSP2115 toolkit, EPROM/EEPROM programmer under Windows NT/95, UNIX and summary of macbeth Sun Solaris environment. Digital Logic Design VLSI/ASIC/FPGA Design ASIC/FPGA Verification EDA Tools Simulation and Synthesis tools Design verification using VERA HVL. Hardware Description Language: VHDL, Verilog Design Tools: Modelsim, VCS, SPICE (TI-SPICE), ADSP 2115 toolkit Verification Tools: VERA Hardware Verification Language (HVL) EDA Tools: Synopsis Design Compiler, Xilinx FPGA Foundation series, Cadence artist Protocols and Standards: Digital wrapper (ITU-T G.709 standard) for FEC in 10GWANPHY, SONET OC-3/3c and OC-192, PCI Bus Interface, ATM, Ethernet, Transition Minimized Differential Signalling (TMDS) for euthanasia oregon, Flat Panel LCD Monitors Languages: C, C++, PERL Operating System: Sun Solaris 2.1, Windows NT/98/95, Unix, MS-DOS Hardware: 10GWANPHY optical board, HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205), MPC8260. March 2001 - Till date.

Digital Wrapper FEC (ITU-T G.709) Optical Channel Overhead Processor FPGA for 10GWAN. Developed 10GWANPHY (10Gbps WAN) optical board which provided a complete switching fabric solution for Optical Wide Area Networks to support OC-192 Digital wrapper transmission standards (as defined by ITU-T G.709). Developed architecture and coded Transport OverHead (TOH) FPGA which interfaced with HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205) devices and MPC8260 Motorola Power PC via its Local Bus. HUDSON is fully integrated with Variable Rate Digital Wrapper Frammer/Deframmer, Performance monitor and Forward Error Correction (FEC) device developed by Advanced MicroCircuits Corporation (AMCC). KHATANGA is a dense VLSI device developed by Advanced MicroCircuits Corporation (AMCC) that integrated a 10GbE MAC, a 64B/66B Physical Coding Sublayer (PCS) and a WAN Interface Sublayer (WIS) as baselined by IEEE P802.3ae task force. Used this FPGA to configure HUDSON through its microprocessor interface port, control and monitor status of euthanasia, Optical Channel Overhead bytes/Sonet Overhead bytes (Transport overhead and Section overhead of is jeffrey dahmer, OC-192c frame) in data channels of HUDSON and to support all Insert/Drop Overhead Channels of HUDSON and KHATANGA. Defined 16-bit Register Memory Map inside this FPGA with predefined memory locations for Parallel 8-bit Overhead Insert/Drop channels of HUDSON (both Encoder and Decoder sides) and for serial Insert/drop Channels of Hudson and KHATANGA. MPC8260 wrote overhead byte information into FPGA memory locations defined for euthanasia, those particular interfaces, which will later be inserted into insert channels on the next frame. On Drop channels FPGA collected Overhead byte information and stored them in internal predefined memory locations that will be later read by MPC8260. FPGA also monitored all status pins of HUDSON device like Loss of Clock, Out of theory of caring, Frame, Bit Parity Errors (BIP) and reported them to MPC8260.

Implemented FPGA on Xilinx Virtex XCV200E series (FG456 package) and implemented all dual port RAMs using 28 Block RAMs available inside this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of the chip. Automated critical parts of is jeffrey, design verification using VERA HVL. Coded MPC8260 local bus, HUDSON and KHATANGA interface modules in Verilog HDL using VI Improved Editor (Vim). Simulated functionality using ModelSim (Modeltech_5.5). Involved in synthesis of modules using Xilinx FPGA tool. Environment: Verilog HDL, VERA HVL, VIM, ModelSim, Xilinx FPGA Foundation series, Windows NT. Contesse Semiconductor Corporation.

October 2000 - February 2001. SONET Transport Overhead Processor FPGA (OHP155) Designed an FPGA as part of GigaStream Switch fabric chipset for collecting and oregon transmitting overhead bytes (both Transport overhead and alive Path overhead of SONET OC-3/3c frame) to/from optical interface. Developed architecture and coding of SONET Over Head Processing (OHP) FPGA interfaced with Spectra155 interface, High Capacity Multi-Vendor Integration Protocol interface (HMVIP) and CPU interface. Spectra interface consists of Transport OverHead (TOH) and Path OverHead (POH) interfaces to transmit and receive directions from Spectra chip. Four Optical Switch Processor 155Mbps (OSP155) cards shared a single HMVIP interface in a Time Division manner. The CPU interface is a Network Switching Processor (NSP) CPU interface to OHP FPGA for configuring. TOH/POH overhead byte information collected on HMVIP side is oregon, sent to corresponding Spectra155 devices. Similarly overhead data that is sent by Spectra155 device is sent to HMVIP interface in correct time slot at correct frame location.

There are eight dual port asynchronous RAMs implemented in essay this FPGA. Analyzed system requirement specifications and developed architecture for oregon, full functionality of chip. Coded transmit side modules of by William Essay, this architecture in euthanasia Verilog HDL and tested functionality and performance. Judgment Essay. Developed self-checking testbenches that automatically generated reactive tests using VERA HVL. Used Xilinx synthesis tool for synthesis of design and euthanasia oregon generating sdf file. Did post-synthesis simulation of this design. Environment: Verilog HDL, VERA HVL, Modelsim, VIM, Xilinx FPGA Foundation series, Windows NT. Contesse semiconductor Corporation. April 2000 - September 2000. Designed an FPGA to convert Fusion Omni-Connection for oregon, Universal Switching (FOCUS) bus interface to Packet on SONET physical interface (POS_PHY) bus interface, so that Vitesse s VSC9112 (OC-48) chip could be interfaced to Vitesse s Network Processor IQ2000 through this FPGA chip.

Designed in Xilinx Virtex-E XCV-300E FPGA. This FPGA had FOCUS 32 bus and POS-PHY-3 bus on either side to convert data (packets) from one bus protocol to other. Multiple packets can be processed in both transmit and receive directions. Used two FIFOs in Ping-Pong mode to carry Fcells in both receiver and transmit side. Did regression testing of Verilog RTL code. Oregon. Generated random set of valid test cases using a seed value. Used Turbo C for writing a C code, which automatically selected a random number of test cases from the is jeffrey valid testcase library using a seed value. Environment: Turbo C, Verilog HDL ModelSim, SignalScan, VIM, Windows NT. December 1999 - March 2000. Timing Controller Chip with mini-LVDS and FlatLink. Designed a Timing Controller Chip for Thin Film Transistors (TFT) LCD flat panel monitors with MINI-LVDS (Low Voltage Differential Signaling) and Flatlink interface.

This chip id designed for oregon, customers like IBM, Samsung, LG with programmable display resolutions ranging from XGA to UXGA and to even support SXGA+ and W-UXGA. Chip interfaces with CPU display card using TMDS (Transition Minimized Differential Signaling) Flatlink standard for by William Shakespeare Essay, digital transmission of Video output data at 1.56Gbps, also it interfaces with LCD drivers through MINILVDS analog interface standard. It also generates autogreying patterns automatically to test LCD monitor. Involved in digital architecture design of euthanasia, chip. Coded the entire architecture in VHDL and did functional testing and simulations of code. Used Shell Scripts for taking test bench (testing file used to test functionality of VHDL code). Used Synopsis DC for synthesis. Performed post-synthesis simulations. Tested and by William Essay verified actual performance of chip on LG s LCD monitor. Environment: VHDL, ModelSim, Synopsis DC, Advanced Norton Editor, Sun Solaris 2.1. May 1999 - November 1999.

Design of Flying Adder Digital Logic for euthanasia, PLL (TFP8501) Chip. Designed a Scaler chip for LCD flat panel monitors to support resolutions upto SXGA+/UXGA and to maintain compatibility of various video cards and is jeffrey still alive LCD monitor resolutions by upscaling or downscaling resolutions whenever required. Involved in design of Digital logic for Flying Adder PLL (50MHz to 350MHz). Did coding of digital logic in VHDL. Performed synthesis of design using Synopsis DC. Used SPICE for analysis the analog behaviour of euthanasia, timing critical nets. Interfaced logic with analog PLL using SPICE. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, TI-SPICE, Sun Solaris 2.1. January 1999 - April 1999. Design of essay, Analog PLL. Involved in the design of a TMDS receiver chip with HDCP for LCD flat panel monitor to support Transition Minimised Data Signaling protocol with High Data Content Protection.

Rate of video data transfer on TMDS channel is 1.6Gbps. It enabled data interaction between CPU monitor video card and LCD monitors to be entirely digital. Designed architecture of Analog PLL (65MHz to 250MHz). Did Analog circuit design of oregon, Phase Frequency Detector (PFD), Charge Pump, Bias Generator and VCO. Used Cadence Artist and Spice for analog design. Carried out all process corner simulations of individual design modules and completed closed loop simulations of PLL.

Environment: Cadence Artist, SPICE, SimG, Sun Solaris 2.1. October 1998 - December 1998. Power Management Module for TFP401 Chip. Involved in the Design of jackie robinson, a TMDS receiver core chip for LCD monitors. It supports Transition minimized Data Signaling protocol from euthanasia oregon, PC Video cards to LCD monitor.

Chip enabled data interaction between PC monitor video card and LCD monitors to be entirely digital. Euthanasia. Designed and coded the architecture for Power Management Module in VHDL. Did synthesis of watsons, this module. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, Sun Solaris 2.1. Mignion Systems Limited. July 1998 - September 1998.

Design of euthanasia, Single Phase Energy Meter. Designed and developed an Energy Meter architecture using ADSP2115 digital signal processor that calculates voltage, current, power, power factor, frequency and does harmonic analysis. Did assembly language programming of design. Successfully tested design on power lines. Environment: VI editor, ADSP2115 toolkit, EPROM/EEPROM Programmer, Windows 95. M. Jackie. S. in Microelectronics and VLSI Design. ASIC/FPGA Design Verification Engineer. 2.6 years of experience in FPGA Design ASIC Verification.

Proficient with coding RTL Behavioral using Verilog and VHDL. Proficient with developing test environment for functional verification. Proficient in developing appropriate test vectors using Verilog,VHDL,Vera and e language. Proficient in writing fully automated test benches. Experience with synthesis and optimization of Verilog/VHDL code Experience with FPGA implementation with Xilinx. Worked on Mentor Graphics Synthesis tool - Leonardo Spectrum, Synplicity Synthesis tool Synplify Worked on different simulator tools- Verilog-XL(Cadence), Modelsim(Modeltech) and VCS(Synopsys).

Worked on Mentor Graphics Schematic Entry Tool Ė Design Architect. Worked on PCI 32 bit @33Mhz Worked with Specman, an ASIC Verification tool from Verisity Familiar with Vera, an euthanasia, ASIC Verification tool from Synopsys Familiar with DSL Protocol. Familiar with ATM Protocol. Familiar with AMBA Bus Architecture. Familiar with 8085 and 8086 Architecture.

Familiar with 8085 Assembly Language. Familiar with software languages C and essay Fortran. Euthanasia. Good communication skills. ABC Chips Inc, San Jose, California. FPGA Design Verification Engineer. Name of theory, Project: Network Processor Verification. Wrote test plan for one of the modules in the chip.

Developed the oregon test bench for Fresco Essay, the module. Euthanasia Oregon. Wrote test cases in Verilog. Developed the different interfaces around the module. This network processor is designed to provide solution for 10 Gb Ethernet, OC-192 applications. Michelangelo's Judgment Essay. The ingress device supports a POSPHY Level 4 (PL4 ) interface and the egress device supports CSIX interface to a switch fabric. Tools Used : VCS Modelsim. Language Used : Verilog. Name of Project: Link2 Mask Pattern Generation FPGA-SDRAM Controller FPGA.

Designed and euthanasia Synthesized SWATH cycle Controller module. RTL coding done in Verilog with Verilog-XL and Synthesized using Synplify Developed the different interfaces around the Fresco The Last Link 2 FPGA. Developed test plan for the functional verification and euthanasia wrote test cases in Verilog. Still. Done the module level verifications and top-level verification. Reported bugs and worked with the design team in fixing the bugs. This module does interface controlling from the input side and takes the processed data to and from SDRAM controller. Oregon. This module also does the interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and SWATH FPGA. . This module does interface controlling from the input side and oregon takes the processed data to and from SDRAM controller. This module also does the iron significance interface to the output swath FPGA.

This Link2 acts as a link between the input FPGA and SWATH FPGA. Tools Used : Verilog-XL (Simulator),Synplicity (Synthesis tool). Language Used : Verilog. Silicon Grafic Systems, Bangalore, INDIA. IC Design Engineer. Name of Project: Rrishti-1-Trace Receiver ASIC Verification. Handled the responsibility of verification of all NRT transfers using IBM(Internal Bulk Memory) at oregon module level and device level. . Wrote test cases in euthanasia 'e' language and verified them using Modelsim simulator. Reported several bugs in the design and worked with the designers to fix those bugs. The is a trace receiver, which provides the trace recording capabilities for one of the Emulation controller. The key features of the trace system ASIC are:

Provides a maximum of theory of caring, 4 channels operated at single edge clocking (positive edge, negative edge, positive edge and negative edge, or alternatively 2 channels operated with Bi-phase clocking scheme. Oregon. An optional off-chip trace memory of a minimum of 128 M x 32 words provided by an EMIF(External Memory interface) using 64 bit SDRAMS serving all four channels. On-chip trace static RAM memory organized as 32k x 64 (ie.256 bytes) serving all four channels. This memory is used as channel temporary buffers and scratch memory when SDRAM is watsons of caring, used to store channel data. Euthanasia Oregon. trace packet width from dahmer alive, 1 to 20 bits 167 MHz processing rate. The trace peripheral has two distinct sections ,a front end and a back end. The front end (TPFE)acquires the trace data presented by the target and packs this data efficiently into 64-bit words. The Trace peripheral back end (TPBE) dispositions this data to trace memory, managing buffer locations, lengths, and host access to these buffers independent of whether the storing process is active. In short, the euthanasia oregon TPFE contains the acquisition, packing and buffering functions while the TPBE distributes the jackie robinson essay TPFE generated data into Trace buffers. Tools Used: Modelsim (Simulator),Specman Elite (ASIC Verification tool). Language used : VHDL (RTL), e language for test cases. Engineering Design Center , Bangalore, INDIA.

Hardware Design Engineer. Name of watsons of caring, Project : PCI based high speed data acquisition card for euthanasia oregon, signal Processing. Designed the Hardware . Designed the Michelangelo's Fresco The Last Essay FPGA CPLD . Done the euthanasia oregon functional simulation synthesis. Done extensive timing simulation with back annotating the sdf. Done schematic Entry using Mentor Graphics Tool. PCI Add on card with PLX 9080 as PCI Bridge and on the local side uses one FPGA , which does all logic including bus arbitration and of caring data transfer to FIFO . It actually acts as a local processor to PLX 9080. The input to the card includes 16-bit parallel data stream with strobe and 100 Mbps serial streams. Only one of these may be activated at a given time. The design goal is to accept data rate upto 40MB/s, but the act 2 testing will be limited to 20 MB/s transfer to memory.

FPGA we were using was Spartan series XCS 40-4 ns. VHDL entry, compilation and functional simulation is done through Model SIM a front-end tool, then after this we had done synthesis through Leonardo spectrum. From that some edf(edif) files are generated and we open those files in the Xilinx tool. Euthanasia Oregon. We are using Xilinx tool as the back end. Here we place and robinson essay route the design and euthanasia oregon generate timing simulation data. From there one sdf(standard delay format) file is generated.

This includes all the internal delays of the device. The Xilinx tool also generates a test bench file. We will apply our stimulus to that Test bench and we make that as the test bench for euthanasia, timing simulation. . So when timing simulation comes we load our design file and oregon the sdf file and theory of caring simulate. Usually the FPGA has to be configured using a serial EPROM. But in our case since the FPGA is being configured from the system side, it cannot be a permanent data as from euthanasia, EPROM. So we are using the CPLD to configure the watsons theory FPGA. It will take data through the local bus and oregon load it to the FPGA. Tools : Modelsim (Simulator),Leonardo Spectrum (Synthesis), Xilinx Design Manager (Place Route). B.Tech Final Year Project done at ER DCI , Tvm, Kerala, INDIA. Project Title: VHDL Model of Michelangelo's Fresco Essay, UART.

Developed the architecture Designed and euthanasia done RTL coding in jackie robinson VHDL. Done the functional simulation, synthesis and mapped to the target PLD. Tool Used : WARP 4.1. Simulator used : NOVA. Host Platform : PC under Win95. Device Mapped : CY7C341 from Cypress ( 192 Macrocell EPLD) Study in detail one Standard HDL Study in detail about the PLDs Write own HDL code to build a model of one Standard UART chip with defined requirements Simulate the code for euthanasia oregon, functional verification Synthesize and map the design to a suitable PLD. 10.1995 - 05.1999 Degree : c Major in : Electronics and Communication Engineering University :M.G University Kerala, INDIA . Got an award from Silicon Automation Systems ,BANGALORE for being the robinson best project team for the quarter of the year 2000 for euthanasia, the Rrishti-1 Project. Got an award from the customer( Texas Instruments,Bangalore) for Fresco Judgment, outstanding Performance valuable contribution to the verification of Rrishti-1. Doing part-time courses in San Jose University for.

Course 1- Advanced Logic Design (Winter 2001) Course2-VLSI Design I (Winter 2001). Course3-Logic Design using HDL- Project- Bluetooth Transmitter. Course4-Logic Synthesis- Done using Synopsys DC. REFERENCES : Can be provided based on request. Seeking a challenging position in VLSI design and/or verification where my skills and experience will greatly enhance the company's success and my personal growth. H/W Description Languages: VHDL, Verilog. Place and Route: Lucent OFCC (ORCA Foundry Control Center), Altera Quartus, Xilinx Alliance. Synthesis: Exemplar logic (Leonardo Spectrum). Simulation: Modelsim, Quicksim from Mentor Graphics, VCS from Synopsys, VirSim (graphical user interface to VCS for summary of macbeth act 2, debugging and viewing waveforms). Others: Mentor Graphics DA, Autologic II, Visual HDL, Renoir.

Languages: C, C++, perl, Unix Internals like Shell and euthanasia oregon Awk. Operating Systems: Solaris 5.6, FreeBSD 2.2.6, Windows NT/98. Networking Protocols: TCP/IP, UDP, ICMP, NIS, NFS, RIP, OSPF Others: PCI. Revision Control: CVS. Saristos Logic Corporation, Mountain View, CA. Consultant, ASIC Engineer. As an ASIC Engineer, was a key individual contributor on a team responsible for conceiving, planning and implementing software and hardware systems required to validate Storage Area Network (SAN) systems. Storage Area Network (SAN) offers simplified storage management, scalability, flexibility, availability, and improved data access, movement, and backup.

Worked closely with the ASIC and hardware development teams with the goal of delivering quality ASIC silicon for advanced storage. Register/memory access via PCI cycles or PCI DMA transfers or RTL hierarchy. Developed ASIC verification strategies for CSC Custom Logic, CAC Custom Logic, EPIF Data Windows, EPIF Interrupt Controller, DMC Scan Engine, EPIF thrasher Sim that span simulation, hardware emulation (FPGA), and real-silicon environments. Wrote ASIC verification test plans that encompass ASIC block-level, full-chip and SAN sub system-level functionality. Analyzed, designed, developed code, documented, and tested ASIC verification test suites using VCS Synopsys and System c . Migrated test suites developed in the Verilog simulation environment to both hardware emulation and euthanasia final silicon lab verification environment. Each Verification Sim was tested with a model which also takes the same input vectors and generates expected value for summary act 2, that input vectors. The expected Value is checked with the RTL value to verify the functionality of each block. Wrote high level monitors and stimulus models to automate the verification process. Euthanasia. Analyzed the timing for Data Windows using Logic Analyzer thus reducing the time for Data Window writes from 1.5 hrs to 18 mins for oregon, 1GB of Othello, Shakespeare Essay, memory on Hardware Emulation Platform.

Wrote Scripts for HEP (Hardware Emulation Platform) regression suites. Participated in estimating verification development schedules and ensured on time delivery. Infotech Systems Inc., Boston, MA. As a Design Engineer was responsible for Michelangelo's Fresco The Last Judgment Essay, conceiving, designing, developing and testing digital circuits for both ASIC and FPGA. Designed and tested the digital portion of the euthanasia chip for Essay, television. Responsible for oregon, complete cycle from specification through design and robinson test. Designed the digital circuit using VHDL. Synthesized using Leonardo Spectrum, targeting it to Lucent's ORCA series FPGA. Developed simulations with VHDL and euthanasia simulated it in Modelsim generating the test vectors for testing the FPGA. Dahmer Still Alive. Developed Verilog testbenches and tested the circuit back annotating with SDF.

Checked the timing of the design generating test vectors for testing the ASIC. Oregon. Designed and tested Inter-Inter Connect (I2C) circuitry in VHDL and Michelangelo's Fresco The Last Essay Verilog using Visual HDL. I2C bus defines a serial protocol for passing information between agents on the I2C bus using only a two pin interface. Designed a I2C bus slave interface controller using Visual HDL. Synthesized the euthanasia oregon circuit using Leonardo Spectrum and targeted to Lucent's ORCA series FPGA.

Developed test benches in VHDL for summary act 2, testing the proper working of the design using Modelsim. Euthanasia. Designed and tested the read channel chip. Worked on three different versions of the essay read channel. Designed the FPGA using Visual HDL generating the RTL for the design. Euthanasia Oregon. Tested the design writing VHDL test benches for the proper operation Placed and routed the design using ORCA Foundry Control Center targeting to the Lucent's ORCA series FPGA. Evaluated place and of macbeth act 2 route tools for the read channel chip.

Evaluated the euthanasia design to test the read channel chip with various FPGA place and route tools. Euthanasia. Tools evaluated include Xilinx's Alliance, Altera's Quartus tool and of caring Lucent's ORCA Foundry Control Center. Designed and tested the Test Access Port (TAP) controller using Visual HDL. Designed an IEEE standard TAP controller. Euthanasia Oregon. Generated VHDL code from Visual HDL and tested the controller by writing test bench in VHDL. Simulated it using Modelsim. Developed Perl script for , conversion of Spice netlist in to VERILOG netlist. The script written in perl takes in a Spice netlist and gives the Verilog netlist. Oregon. Developed testbenches for the Verilog netlist for the million-gate chip. Developed test sequence for this verilog file for checking the operation of the chip.

Master of Science, Electrical and Computer Engineering, Southern Illinois University Edwardsville, January 2000. Relevant course work includes Digital VLSI Design, Digital Computer Architecture, High Performance Architecture, Analog VLSI Design, TCP/IP Inter Networking, C++ Programming. Structural and Behavioral RTL description of a Simple Educational 16 bits Processor in Verilog. The structural description of the data unit, the control unit, SRAM and other modules were coded and tested. Other Projects Design of a Linear Interpolation Filter using Verilog and Fresco The Last full custom IC layout. Design of euthanasia, a Simple Educational Processor using VHDL.

Designed and is jeffrey simulated a sigmadelta modulator for an EEG IC. Bachelor of Engineering, Electrical and oregon Electronics Engineering, University of Madras, May 1998. Reference: Furnished upon request. ASIC-FPGA Design Verification Engineer. To work where I am given the opportunity to assionately exploit my knowledge to the fullest level of satisfaction both personally as well as for the company I serve on the whole. SUMMARY OF EXPERIENCE: Over 7+ years of euthanasia, experience 5+ years of of macbeth, experience in euthanasia Hardware Design, Development Verification using ASIC, PLD, CPLD FPGA Designing Verification, Board simulation, ANSI C, Assembly, C++, PLI, PCI, VLSI, PCB, Verilog, Synopsis, VHDL,VERA, Gigabit Ethernet,(Networking) SONET,ATM, Device Drivers , Win Board, Synthesis, Verification of Design.CMOS,Embedded System (SOC),Real Time Operating System RTOS), VxWorks, Logic Analyzer, Simulator, Emulator Programming of RAM(SRAM DRAM) With excellent analytical and programming skills. Very conversant in summary of macbeth documentation, presenting prototypes, client interaction, quality assurance. Good communication and interpersonal skills.

Strong Points include quicker grasp to new concepts, the oregon ability to pursue matters in great detail and able to work in a team. Bachelor of Electrical Engineering from euthanasia, Bangalore University. Jan 2000 - Present DSSABC Software, Inc., CA, USA. Feb 1998 - Nov 1999 FDD Containers Limited, London, UK. Oct 1996 - Jan 1998 RANDY ENGINEERING, Tripoli, Libya. Jul 1994 - Sep 1996 Advanced Systems Solutions, Delhi, India. Client: Smart Networks Utilties, Santa Clara, CA Aug 2000 to Present. Scope of the project was to design develop a micro controller chip for networking purpose on networking boards, which sends and watsons theory receives data digitally Supports Gigabit Ethernet on Fiber Optics. My Role: As a team member I was involved in. FPGA ASIC design Wrote verilog HDL code for design. Oregon. Wrote test bench for verification in C Used PLI for communication with Verilog.

Integration testing verification. Functional testing verification. Environment: Verilog HDL , Xilinx-4000 Series , Win Board , C , PLI , ATM, VxWorks , Synopsys. Client: Digital Design, Santa Clara, CA Jan 2000 to Aug 2000. The objective of this project was to design, developed the data networking boards and test benches for verification purpose of pre written functions in verilog . Simulation and hardware development of communication subsystems using the sections reconfigurable-prototyping.

Design, simulate, and test digital hardware. Developed data networking boards, and backplanes. Performed the design, capture the euthanasia oregon schematics and theory of caring oversee the board layout. Performed board simulation and signal integrity. Environment: Verilog HDL , Xilinx-4000 Series ,VERA, Win Board , C , PLI , VxWorks. FDD Containers Limited, London, UK [Feb 1998 - Nov 1999] Project: DSP Motion Controller 09/98 to 11/99. Client: FDD Container (UK)

The purpose of the project was to design and develop micro controller chip 80188EB for controlling the euthanasia motion of Mechanical Equipment Boomer there was servo motors which controls Boomer Motion.Servo Motor was controlled by the tech called DSP motioncontroll (Digital Signal Processing). The RTOS was designed implemented on higher priority algorithm, the signals of higher priority is jackie essay, served earlier than a signal with lower priority. The code was written in euthanasia oregon c inline Assembly on Host Computer. Design, simulate, and test. Programming of SRAM DRAM. Writing Test Benches for Verification in verilog C. Euthanasia Oregon. Performed board simulation. Environment: C, ASIC, Test Bench for Verification, Perl, Synthesis, Verilog, Inline Assembly, Target 80188EB,RTOS VxWorks.

Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. Project: Micro controller Development (Embedded System) For Geo Systems 02/97 to 09/98. The purpose of the euthanasia project was to design and develop micro controller chip 8051EB for controlling heat Generation in Turbines of thermo electric Power plant. The processor controls the steam temperature. Which receives the signals from Boiler sensors. If due to any reason the temperature goes below specified level the alarm will be activated. It had the provision of printing the Time versus heat graph controlled by the processor 24/7.Programming of the RAM was done by c inline assembly. Device programmer was used to copy the image files on the chip. Design, simulate, and test micro controller chip. Euthanasia Oregon. Programmed SRAM DRAM. Wrote verification code in verilog C Performed the design, capture the schematics and iron oversee the euthanasia board layout.

Performed board simulation. Environment: ASIC Design, VHDL, Verification, Test Bench, C, PLI, Inline Assembly, Perl, Target 8051, RTOS PSOS, Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. RANDY ENGINEERING Tripoli, Libya [Oct 96 - Jan 97] Project: Material Management System 10/96 to 01/97. DOS based Stand alone Database Application developed under C++ for Civil Engineers providing Menu Driven User Interface for calculating the Quantities of material required and its Costing, providing an easy access to feed the User input data. Michelangelo's Fresco. Its related Quantity and Cost will be calculated automatically with the help of in-build functions related data Information that is also capable of modifying as per the user specifications and standards.

It takes the Complete Details of a building (to be constructed) by euthanasia providing an theory, Interface and Calculates the quantity of material required with its estimated cost, as per the standards specified. It provides an easy access for modifications. Environment: C, UNIX and MS DOS. Smart Systems Solutions, Delhi, India [Jul 1994 - Sep 1996] Project: Employee Scheduler Management Jan 96 - Sep 96. A standalone Application developed using Visual C++ 5.0, for Microsoft Windows95 and euthanasia oregon Microsoft Windows NT, to be used as the Employees Schedule and its Related Information, in a Large Companies, Hospitals etc. Developed system allows you to get detailed Information with Graphical Representation related to an employee and its Schedule (Working and summary of macbeth act 2 Leave Duration's Designed for oregon, a Complete year) Allows Online Modifications for Updating the Individual Schedule of an employee, and its related information. Is Jeffrey Dahmer Alive. Which intern Automatically updates the related Schedules of other employees if desired. Environment: Visual C++, MS Windows 95. Project: Management and Security of File System Feb 95 - Jan 96. An Application Program of euthanasia oregon, which the Core Part is handled using C++, and dahmer the GUI (Graphical User Interface) is handled using Visual C++ for Microsoft Windows 95 and Microsoft Windows NT.

Which allows the user to maintain its File System with Security, providing File and Application Locking. With which it is possible to lock any Executable Program from being unauthorized Access, by providing Password facility. It is euthanasia oregon, Capable of Locking Windows95 from being Loaded Unauthorized at the Boot time. Provides an Easy and Quick File Search. Provides Quick Access to file Opening and Executing.

Provides File Viewing facility before editing the files, giving an oregon, Easy access to Editing. Environment: Turbo C++ 3.0, Visual C++ 5.0, and MS Windows 95. Project: Standard Product Impress Jul 94 - Feb 95. Impress is a standard integrated package targeted at the Printing and oregon Advertising Companies as the major customers. It was designed and developed by Thomson Technologies, India. The product included modules such as Financial Accounting, Purchase, Sales, Inventory and Production (Studio Section Camera Section). Was a member of the watsons of caring team, which designed the euthanasia system? Other responsibilities included coding and testing. Developed 12 forms and theory of caring various other Reports. Environment: Visual C++, Visual Basic, MS Windows 3.1. Visa Status : H1B.

References: Available on request. Nine and a half years of oregon, strong experience in Verification of ASICs using Verilog, VHDL, VERA, Verilog -XL, Synopsis VCS, Mentor Graphics Co-Verification Environment, Assembly Language on Unix platform. Theory Of Caring. Expertise in writing Verilog Model, developing test plans, Quick test writing and oregon setting up Verification environment in Verilog/VHDL. Good knowledge of PCI protocol. Hardware Description Languages: Verilog, VHDL High Level Verification Language: Synopsis VERA CVE: Mentor Graphics Co-Verification Environment Simulation Tools: Verilog-XL, Synopsis VCS, Veriwell Languages: Assembly Language for Intel MCS 51/Motorola MC68000/MIPS processor/ ASM 51 Assembler and Linker/in circuit emulator 51, C OS: Sun Solaris, Unix, Windows 95/NT. LSX Technology, Inc., Moutain View, CA. August 01 till date. Verification of PCI bridge( PCI to local) PCI 9656. Wrote random tests for the verification of the PCI 9656 for Direct Slave . Direct Slave means that the chip is the jackie slave on the PCI bus, Direct master means that the euthanasia chip is the master on the PCI bus. Worked on PCI compliance testing for of macbeth, the PCI 9656 using Synopsys PCI compliance suite.

Worked on FIFO testing. There were 2 FIFOs. Oregon. One for the Direct slave read and the other for Michelangelo's The Last Essay, the direct slave write. Wrote various test and euthanasia verified the functionality of the FIFOs for both the empty and full condition. Jackie Robinson Essay. There were numerous condition to fill and empty the FIFO. One such condition could be no grant on the local side or on the PCI bus for the external master. Oregon. The chip has 3 modes namely M, C and J modes . These modes are the local bus types.

M mode is 32 bit address/32 bit data, non multiplexed direct connect interface to MPC850 or MPC860. C mode is 32bit address /32 bit data non multiplexed for intel processor i960 and J mode is 32 bit address/32 bit data multiplexed. Environment: Verilog, Sun Solaris. Visitor Graphics Corporation, CA. January 01 - till date. Field Application Engineer. Was responsible to give product presentation, demonstration for iron curtain significance, the Seamless CVE (Co- Verification Environment).

The Hardware and Software Co- Verification helped in software debugging, shirk the system integration time and avoid prototype respin. Was required to perform evaluation of the product at the customer site. Satisfied the euthanasia customer about the utility of the product through a question/answer session and euthanasia with follow up visits to potential customers. Performed evaluation of the product and against the product of alive, competitors. Environment: Verilog, CVE, Assembly, Sun Solaris 2.x. Advanced Networks, CA. December 99 - December 00. Verification of a Packet Classification ASIC. The ASIC was used to offload the euthanasia network processor of the job of classification of the packet. The packets could be classified on the basis of the header or any byte of the data payload.

The ASIC had system bus interface, ERAM interface, AOC PIB modules. The interface of the chip was like memory so supported both zbt and non zbt modes. The system bus could be configured as 64 bit or 32 bits. The speed of the ASIC was in oregon the range of 50 - 100 MHz. Wrote diagnostics to verify the system bus interface using Verilog.

Build the Chip Verification Environment using VERA. Watsons. Debugged the failing test cases. Found several bugs and fixed the bugs. Environment: Verilog, VERA, VCS, Sun Solaris 2.x. June 99 - November 99. Verification of a Networking SOC. Involved in Verification of euthanasia oregon, a Networking SOC having MIPS Processor, SDRAM Memory, MAC, PCI and HDLC. Was responsible for Verification of the bridge between the MIPS Processor and the Toshiba Proprietary bus using Assembly and watsons theory Verilog in a multi master System Verification environment. Developed several MIPS Assembly and oregon Verilog based test to verify the jackie robinson functionality of the G bridge and HDLC.

Translated the unit level test cases for euthanasia oregon, HDLC to system level tests. Verified the tests at full chip level. Found bugs, notified the designer and suggested fixes. Environment: Verilog, Assembly, VCS, Unix. January 99 - May 99. Verification of act 2, a Network Output Controller. Network Output Controller was responsible for moving data (packet) from the packet buffer (external SRAM memory) through the port FIFO s to the network interface.

Verified the euthanasia oregon above functionality of the NOC by writing the functional models in Verilog. Verified functional models. Verified Packet buffer read and writing. Packet buffer was read and Fresco Essay written as 1024 bits at oregon a time in 11 clock cycles. Verified the packet Queue (PQ) which performed queuing and dequeuing of the packet through the star address in PB and the skip over mask. Jackie Robinson. Verified Packet Receiver which received packets from all the 50 ports at the network interface in the TDM manner. Functional model of the NOC was written before the RTL could be plugged with other functional models. RTL replaced the NOC model. Developed the test bench and wrote task for euthanasia oregon, specific functionality. Developed test plans, test cases for by William Shakespeare Essay, the Chip Level Verification of the oregon ASIC using Verilog. . Found and fixed bugs.

Environment: Verilog, Verilog -XL, Sun Solaris 2.x. March 98 - December 98. Design and Verification of HDLC Controller (Project Lead) Involved in Design and Verification of HDLC Controller with a generic 8- bit microprocessor interface. Euthanasia Oregon. The HDLC controller framed according to the HDLC protocol. The frame checksum generator and checker were implemented. The controller was to the ITU Q 921 specification. . Designed the HDLC controller. Involved in portioning of the design into Transmitter and Receiver. Verified the HDLC.

Synthesized the HDLC. Environment: Verilog, Verilog-XL, Sun Solaris 2.x. Sonet Technologies Pvt Limited. January 97 - February 98. Development of robinson, VITAL ASIC Libraries. Verilog to VITAL converter was used to translate the Verilog Structural Model to VITAL. Oregon. Testing was done on Quick HDL simulator, which was one of the sign off simulator for LSI logic. Was responsible for Conversion and Simulation. Environment: VHDL, Quick HDL, Unix. Sonet Technologies Pvt Ltd. April 95 - December 96.

Development of Test Bench for BUS Interface Model for MC68030 and MC68020. This was implemented using the Co- Verification Environment developed by Mentor Graphics. The hardware (Verilog/VHDL) was simulated on HDL simulator like QuickHDL and the software was simulated on the software simulator (different for each processor). The Bus Interface Model was specific to the processor and iron curtain significance generated bus related cycles for the processor depending on the type of access. The tool was used in euthanasia designing embedded system where the jackie robinson essay software could be verified against the hardware before the hardware prototype was made. Environment: Verilog, VHDL, CVE for Mentor Graphics, Unix. Parametric Network Limited.

November 91 - March 95. Development and Verification of a Keyboard Controller using 87C51FA Microcontroller. Developed assembly language programs. The keyboard and the system (486 PC) serial communication was established and keys were scanned. Oregon. Whenever any key was pressed, the make and the break key codes were sent serially in an 11-bit format to the system (486 PC). Provision was made for interfacing more than 1 keyboard with this keyboard controller. This also included the standard PC keyboard. Environment: Assembly, Unix. To work in ASIC DESIGN/VERIFICATION - Verilog/VHDL modeling, logic synthesis, logic verification, place route, FPGA and CHIP layout.

VLSI Logic design - Complete design flow from RTL to layout. Excellent in both VERILOG VHDL Proficient with Ethernet (MAC), ATM Utopia Level I II protocols. Complete understanding in architectures of euthanasia oregon, PCI OHCI. . Proficient with USB. Euthanasia Oregon. Knowledge in Unix, Perl and 'C'.

Knowledge in VERILOG PLI CONCEPTS. Iron Significance. Good experience in Digital synthesis and Place Route. Configuring CPLD with bit blaster using MAX+plus II. Euthanasia Oregon. Expertise in Altera /APEX FPGA. Experience in Assembly Language. Euthanasia Oregon. Analyzed circuits using SPICE. Simulation : Verilog XL from Cadence 2.3, Model TECH 5_3pa version (VHDL Verilog), Leapfrog Simulation for of macbeth, VHDL Accolade Peak VHDL tools. Oregon. Synthesis : Leonardo synthesis tool from Exemplar, Synplify from Synplicity. P R : Altera MAX+plusII , Lucent , Quarters Tool for Michelangelo's Fresco The Last Judgment Essay, APEX Devices.

Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics. Others : Signal Scan and De-bussy for waveform generations Assembly Language : Programming Logic works, C, PERL,UNIX SPICE, MAGIC IRSIM. 'C' Compiler : Green Hills Software. Company I : Analog Systems, CA. Duration : Jan '00 - Till Date. Designation : Member Of Technical Staff. Company II : Trenton Chip Devices, Inc., CA. Duration : May '99 - Dec '99. Designation : VLSI Design Engineer. Company III : Trenton Chip Devices, India. Duration : May '97 - Apr '99.

Designation : VLSI Design Engineer. Company : Analog Systems , Inc. Location : Santa Monica, CA. Designation : Member Of Technical Staff. Project : AD 6489 Voice Over Packet Solution, Fully Integrated VoP Solution. Duration : August 2000 - Till Date. The Si was taped out on Oct '2001. The Total No. of gates is euthanasia oregon, 1.2 Millions.

It operates on 125 MHz. It's a .18 micron technology. The AD6489 family of packet processors performs voice and data packet processing for oregon, the SOHO (Small Office/Home Office). SME (Small Medium Enterprises and RG (Residential Gateway ) Market. . The features it supports is Layer 3 + Software, Voice and Fax, Signaling, Networking Management, Security, Physical Interface, ATM Support, AAL5, IMA, FR and PPP and Memory support. The AD6489 solution helps the system vendor go to market faster by providing a highly -integrated SoC. The SoC comes with a reference board and complete software solution for euthanasia, both VoIP VoATM based solution. A Powerful Application (API) and plenty of processing power are available for the system vendor to provide differentiated value addition to the system. It is euthanasia, having 3 processors namely Control Processor Engine, Wan Processor Engine Security Processor Engine.

The AHB bus being the iron major interface between these processor and the Peripherals, which includes like (UTOPIA, HDLC, UART, GPIO, USB, SPI). There is an euthanasia oregon, intelligent DMA, which does the memory transactions between memory and the processors. Then for the WAN interface we have 10/100 EMAC and also supports external PCI USB. It has on chip SDRAM controller flash controller 200KB of on-chip memory for voice and data processing. Developed Designed in verilog the intelligent DMA block. Which does all the is jeffrey dahmer still alive major operation for the above chip AD 6489 the euthanasia oregon rams. Created Testbenchs for significance, the blocks like UART, SPI DMA. Developed the verification methods created testcases both normal corner for UART, SPI DMA.

Did the oregon RTL netlist simulation for UART, SPI, DMA. Did the other testing like JTAG, MBIST, EMAC, PCI, USB Testing on the RTL netlist level simulations. Did the random testing for the above blocks at theory the system levels and euthanasia oregon also for the other blocks. Verilog XL from Cadence 2.37 Signal Scan/De-bussy for waveforms. Duration : Feb' 00 - July '00. Designed, developed verified the UMAC in is jeffrey still VERILOG. This s going to be used and cable modem chip. The design was target for APEX FPGA from altera 20K200.

The design basically consists of 5 interfaces. Physical, Data Drain, Encryption engine, Data Fill and Microprocessor modules. The PHY interface can get the data from simultaneously from 8 devices and gives to Data Fill interface via data FIFO. It also stores the relative information in another FIFO called pointer. From these FIFO Data fill interface dumps the data to the memory . Euthanasia Oregon. The data drain gets from is jeffrey dahmer still alive, memory and gives to the microprocessor module. The design operates in euthanasia 3 different frequencies.

The input data is coming at 10Mhz, which is to the phy interface. The microprocessor interface is working on 60 Mhz and the rest of the interface is working on 40Mhz. Verilog XL from Cadence 2.37 Signal Scan/De-bussy for waveforms. Max-Plus II for P R. Synthesis by Syniplify from synplicity. Duration : Jan '00. Implemented the SPI interface in VHDL between SPI and external BUS interface used for IMA. Leapfrog Simulation for VHDL. Company : Trenton Chip Devices , Inc.

Location : Sacramento, CA. Designation : VLSI Design Engineer. Project : Transceiver Subsystem. Duration : Nov'99 - Dec '99. Designed Developed controller for DPRAM (in verilog) which is used get the Data from ATM fpga and feed to the microprocessor. The microprocessor reads the oregon data from dpram which was written by the ATM fpga.

Designed the code in Verilog. Compiled and simulated in MTI Verilog simulator (Model Tech). Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics. Project : Internet Data Storage. Duration : Aug'99 - Oct'99. To store the Data into the Disk Array through the user in the internet.The block gets the data to be written into the disk module from the euthanasia oregon memory for iron curtain significance, which the CPU provides the address. The data with the parity is then stored in the memory. While reading the data, it regenerates the parity and checks with the parity that is read. On error, the euthanasia date is invalidated.

The parity and data are stored in the memory through the interface. DMA is used for reading and writing the data into the memory for burst of transaction. Summary. Developed Designed the logic in verilog which is specific to Disk Module and it provides the oregon following functions: Raid Parity generation Raid Parity verification Raid Parity reconstruction Interface to the Main Memory DMA. Compiled and simulated in MTI Verilog simulator (Model Tech). Duration : May'99 - July'99. The OC3 FPGA communicates using either ATM Cells or POS.

In ATM mode, the data path is between the SAR and the PHY via the UTOPIA slave level 1 to UTOPIA master level 2 interfaces. Utopia1 slave is running on 25 Mhz and data rate is 53 bytes. UTOPIA 2 master is running on 33 Mhz and date rate is curtain, 64 bytes. Oregon. There are two downstream FIFOs and two upstream FIFOs. The FIFOs are used in ping-pong mode alternating FIFOs between ATM cells. No parity or packet error reporting of any kind is supported. Synthesized the OC3_FPGA, which had the modules like Lucent PCI Master and Target. Jackie Robinson Essay. Module ware Utopia Master and Slave. Interface Data Path Between Tetra and SAR. Completed Place and Route of the above project which was mapped with the Orca Foundary Family, of the euthanasia Architecture 3T800 Series. Totaled to 390 numbers of Othello, by William Shakespeare, PFU.

Synplify Syntheses Tool From Synplicity V 5.1.4. Lucent Place And Route Tool Version 9.35. Company : Trenton Chip Devices. Location : Chennai, India. Designation : VLSI Design Engineer. Project : Verification Of USB Open Host Controller. Duration : Jan' 99 - Apr'99. Member in the verification of Open Host Controller, which controls the transaction running on USB bus. It fetches the Endpoint Descriptor and Transfer Descriptor from memory and performs the appropriate action depends on the information from the Descriptor. Euthanasia Oregon. These Descriptor includes the jackie essay information about the device. Developed the PCI Test Bench for OHCI.

Created testcases for euthanasia, the functional verification of OHCI. Host Controller is a device which serves devices attached to the USB bus. It is interfaced to the PCI bus for accessing the system memory. Essay. Designed this core using both VHDL and VERILOG. This design has different types of modules. PCI Master and Target block Open Host Controller block Interface between USB and PCI side Host SIE Root Hub. Project : Design of PCI master/target. Duration : July' 98 - Dec' 98. Designed OHCI compliant PCI master/target function.

Done testing on this module. Carried out synthesis of all these modules using EXEMPLAR LEONARDO. Done Place and Route using ALTERA MAX+plusII. PCI Master initiates transaction on the PCI bus for getting the oregon ED/TD's or data's for USB devices from watsons theory, main memory or updating the data from euthanasia, USB devices to main memory. Curtain. PCI target responds to configuration transaction's and other Bus Master's initiates transaction. Implemented the logic for PCI Target and PCI Master. Tested the whole project using ModelTech simulator. Synthesized the logic using Exemplar's Leonardo tool.

Max+plus II tool is used for Place and Route. Euthanasia Oregon. Mapped the PCI core into the Altera Flex10k30 device. Mapped the USB side core into the Altera Flex10k100A device. Mapping the whole design into ASIC Library and is jeffrey dahmer alive testing is in progress. Euthanasia Oregon. Total gate count for OHCI project is 33,000 gates. Project : Design and verification of , Hearsee-USB Logic. Duration : Jan'98 Jun'98. Hearsee is a video compression chip used to capture active video pixels from the digital camera, scales down to 2:1/4:1 ratio, compress the pixels and deliver the encoded data to the computer through USB. It consists of euthanasia oregon, video camera interface, scalar, a high quality compressor and watsons theory USB interface.

The picture information coming from the camera is processed by the hearsee block. This data is euthanasia, first scaled down by scalar block according to the mode of operation. . This scaled down data is compressed by the compressor block. This compressed form of data is sent through the USB cable. Designed the data flow for the still video capture mode of Hearse Created testcases for the functional verification of Hearsee individually in still, motion capture modes as well as combination of still-live modes Performed simulation in modeltech VHDL simulator. Project : Verification of USB Device Core. Duration : Nov' 97 - Dec' 97. Involved in oregon the verification of a USB Device Core. Project : Design of FIFO.

Duration : Oct' 97. Designed a 8-bit 256 deep FIFO with revert and latch read pointers. Used Model Tech VHDL/Verilog Simulators and Leonardo Synthesis Tool. Target technology was Altera FLEX10K device. Project : Design of a bit stuffer. Designed the bit stuffer in logic works, using VHDL and Verilog. Project : Design of a Traffic Light Controller and is jeffrey dahmer alive Stepper Motor. Duration : Aug' 97. Written an Assembly Language Programme for Traffic light Control and Stepper Motor Controller. Used the add-on card with 8253 Timer and PPI chips along with 8379 for testing of this design. Bachelor of Engineering (Electronics and Communication) 1997.

Madras University, INDIA. Euthanasia Oregon. 7.5 GPA. REFERENCE : Available Upon Request. 1200 Moonlight Dr. Santa Clara, CA 95127. Valid H1-B till 2004. Domain Skills: Micro controller and is jeffrey dahmer alive Microprocessor design and verification. Understanding of communication Protocols. Euthanasia Oregon. Applications: Digital Design Methodology Network Flow, RTL coding, Synthesis, Simulation of full chip and block level designs.

Functional verification of iron, full chip design, Physical design skills at chip level, Physical Verification, Writing Software utilities Languages: PERL and oregon Shell Script, C, HTML CAE Tools: Verilog-XL, NCVERILOG, Polaris, Synopsys Synthesis tools, Cadence Composer, Compass tools, DRACULA for physical verification, TransEDA and HDLScore for is jeffrey still, code coverage, AVANTI tools. OS: UNIX, SUN-OS, and WINDOWS. Network Alliance Corporation. Verification Of a Re-configurable Network Processor (09/01 - present) Client: Crystal Systems, Santa Clara, CA.

Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities require me to write directed tests to verify the tile block and random tests to verify concurrency. Code Coverage Analysis (07/01 - 08/01) Client: Vertex Networks, Santa Clara, CA. My role required me to analyze the Michelangelo's Fresco The Last Essay test vectors from the viewpoint of code coverage, and furnish suggestions to the verification team as per euthanasia, the findings.

Verification Of a Re-configurable Network Processor (02/01 - 07/01) Client: Crystal Systems, Santa Clara, CA. Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities required me to write tests to verify the by William various modules of the chip, e.g. fabric, road-runner bus, code generator. I also did the euthanasia oregon code coverage analysis to optimize the essay test suit for better fault grading. Teriola India Ltd., Gurgaon, India. VLSI Design Engineer. Design Of a CAN protocol implementation (11/00 - 01/01) The Control Area Network (CAN) protocol is used in euthanasia automobiles for communicating between various controllers inside the vehicle.

The project involved converting the latch based design to a flip-flop based design. This process involved major timing issues as latch based design had a lot of cycle-stealing. Responsibilities required me to convert the RTL to flip-flop based design and simulate the design to see there are no issues with the conversion. Finished my part in oregon record time. Design Of a microcontroller (10/99 - 10/00) The micro-controller is to be used in automotive Industry for summary of macbeth, anti-skid braking. It is based on Motorola's Mcore processors. Responsibilities required me to verify, Synthesize and PR the Timer block. This project involved the full Network design cycle, except for RTL Coding.

MARCUS Tech, Bangalore, India. VLSI Design Engineer. Design Of a 16 Bit RISC Processor (08/99 - 09/99) It is a general-purpose 16-bit microprocessor core, designed to be used in DSP engines. The project involved full chip design using Design Reuse methodology.Responsibilities required me to design, verify and robinson synthesize the Program Counter block. Functional Verification of euthanasia oregon, a 16 Bit RISC Processor (02/99 - 07/99) ARC85 is a family of general-purpose 16-bit microprocessor cores, primarily designed for embedded applications. The project involves the theory Full Chip functional Verification of the microprocessor core. The chip was verified using Compass-generated vectors. Oregon. I was responsible for writing the test-bench for of caring, the full chip simulation.

Later, the Compass-generated vectors were used to generate the Verilog format vectors for full chip testing. The work also involved the euthanasia testing of vectors on the netlist generated by the Synthesis tool. Dahmer Still Alive. Netlist to RTL conversion was also part of the project. Redesign of 8-bit Microcontrollers(SPC700 series) for Sony Corp(04/98 - 02/99) SPC700 series is a general-purpose programmable 8-bit microcontrollers originally designed by euthanasia SONY. The project involved the redesign of the whole series from 1.4 Micron technology to 0.7 micron tech. It also involved dynamic to static logic conversion. Euthanasia. Participated as a member of a 3 member team. Redesigned 2 of a series of 4 microcontrollers. The redesigning involved Logic Conversion, Schematic Entry, PNR and Functional Verification at the block level as well as the full chip level. . Played major role in setting up the test environment for the full chip.

Executed the project successfully in the first go. Developed a software utility, indigenously, using Perl Shell scripts to convert the stimulus file from ANDO-DIC 8031/32 format to a Verilog compatible format. Oregon. This saved a lot of expense to the company. Granada Consultancy Services. Assistant System Analyst.

American Express Milleniax Conversion (10/97 - 03/98) The project involved the modification of the existing code for American Express to make it Y2K compliant. The project was divided in various implementation Groups (IG's). Theory. Each IG was responsible for modifying and testing a market. Participated as a member of a 4 member team and later as an oregon, Implementation Group leader.

Training in Software Development Process (07/97 - 09/97) It involved training on different Software Platforms, Programming Languages and Graphical User Interface. It also consisted training on Software Development Methodologies. It also involved a project in C on UNIX to manage an employee database. Advanced Chip Synthesis Workshop (2000) The workshop was conducted by Synopsys Inc. at The Last Judgment Essay Teriola, Gurgaon. It focused on advanced chip synthesis methods. 1997 B.Tech. in Electronics Communication Engg (DGPA 8.28) IT, BHU, Banaras, INDIA. Project : Implementation Of Star LAN using PC-AT (11/96 - 04/97) The project involved implementation of Star-LAN using PC_AT's to connect two labs in Electronics Department of IT,BHU. The process involved PCB design and C coding of device driver for the LAN card.

Sr.chip designer, with MSEE in VLSI, from Nortel Networks, experienced in ASIC, FPGA, HDL, C/C++, ATM, IP 10GE, SONET and oregon RT embedded, applies for ASIC / FPGA design or H/W position. MSEE in VLSI Design, ECE of UNB, New Brunswick, Canada. Ph.D. Summary Act 2. Candidate in Computer-Aided Design Center, China. MSCE in Computer Engineering, WU, China.

BSEE in Electrical Engineering, WU, China. SUMMARY OF QUALIFICATIONS. Skilled in all phases of Front-end ASIC, FPGA design, including architecture development, writing specification, partitioning, RTL coding, function simulation, synthesis, timing analysis. Skilled in Verilog, VHDL and SystemC, Specman, Vera, C/C++ and oregon tools: Synopsys's DC, Primetime, GNU, VCS, Verilog-XL, NCverilog, Modelsim, SignalScan and Synplify, Xilinx. Skilled in board level hardware design, Schematic, Simulation, and PCB in OrCAD, Viewlogic. Rich experience in H/W and S/W co-design for robinson essay, MPU-based embedded application systems. In-depth working knowledge of ATM, IP, MPLS, GE, SONET and related network protocols, and euthanasia VLSI devices and essay theory, ASIC design, CPU architecture, PCI, DSP and euthanasia firmware development. Othello, Shakespeare Essay. Good experience in oregon firmware programming in C/C++ under PC DOS, VxWorks and QNX OS. Some experience in mixed signal CMOS IC circuits design, simulation, layout by Cadence tools.

Excited by Shakespeare Essay the challenge. A team work player with creative, self-motivated, cooperative spirit. I have worked in euthanasia oregon 6 companies and universities in Canada and China in summary of macbeth act 2 the positions of oregon, Senior ASIC Design Engineer, ASIC / FPGA Designer, Lead Hardware Engineer, Hardware Engineer, Firmware Programmer and Fresco The Last Judgment Research Assistants since I graduated as a MS in Computer Engineering in 1988. These positions carry over 4-year real experience in euthanasia oregon ASIC/FPGA/VLSI design, and over 6-year real experience in system and hardware board level development, and oregon 10-year systematic theory studies. My background covers Electronics, Microcomputer, Network, Communication, and Control system. Following are my some ASIC/FPGA hardware and system design experience in curtain significance real world in order: Vegatron Networks, Toronto, Canada.

2001 Oct 1 - present. Senior ASIC Designer, SoC Architecture Engineer. (Permanent full-time) Development of oregon, a System-on-Chip ASIC for a new high-performance switching Router. SystemC, C++, GNU/Visual C++ 6.0, Scripts, High Speed I/O, Verilog, DC, PT, VCS, IP protocols. Developing a high-performance IP routing architecture and interconnection protocol for the 4-million gates ASIC based on multiple IP cores. Oregon. Writing a detailed ASIC design specification for RTL design. Vermax Networks, Ottawa, Canada.

May 2001 - Sept 30, 2000. ASIC / FPGA Designer (Permanent full-time) 10GE Egress Traffic Management ASIC Design. Verilog, Vera, Specman, Tcl, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. RSP2 NP, VSC881 Fabric, MPC 8260, PL4, CSIX, PCI32, 10GE, IP, MPLS, ATM, SONET, POS.

Developing an ASIC, interfaced to network processor, PL4, H/S interconnect and PCI32. It runs in three clock domains:700MHz, 200MHz, 33MHZ. The main clock is iron curtain significance, 100MHz. Bandwidth is 10gigabit/s. Euthanasia. The main functions include frame error check, traffic policing, traffic shape, traffic meter, interface to MAC and of macbeth act 2 network processors. The project supports 0-15 channels, POS, OC3-192, ATM, MPLS, IP, 1-10 GigaEthernet, voice and data traffic. Wrote ASIC specification, defined interfaces and developed chip architecture. Defined and Implemented traffic management algorithms for euthanasia, egress traffic and flow control, Including error check, priority shaping and buffer policing function with optimized structure. Partitioned core-based design and Michelangelo's Fresco Judgment Essay Coded in Verilog at RTL.

Designed core-based PCI application interface and wrote testbench for it. Wrote simulation models and performed min. function verification for each block. Euthanasia Oregon. Wrote simulation models and performed min. function verification for top level with cores. Synthesized with Tcl scripts , and analyzed timing to fix timing issues at RTL and Gate level. Is Jeffrey Dahmer Still. Implementing first version in the prototyping FPGA: XC2V1000-5 FG456 and back-annotated. Euthanasia Oregon. Defined software interface and supported firmware designers to write ASIC driver.

Vermax Networks, Ottawa, Canada. 2000 May - 2001 Sept 30. ASIC / FPGA Designer. (Permanent full-time) OC3 ATM core project: ATM Traffic Executive ASIC Design. DS3 ATM core project: ATM Traffic Executive FPGA Design. Verilog, Vera, DC, PT, Perl, C/C++, Formality, VCS, NCverilog, Undertow, Synplify, Xilinx, VisionICE for MPU 8260, Adtech and Smartbit Traffic Generator, HP Logic Analyzer, Scope. Deveopled a chip as an ATM traffic scheduler. It works as part of MMC fabric chipset. It runs in two clock domains: 50MHz and 20MHz.

Total 512 traffic schedulers are required. Successfully developed, implemented and tested the chip in the Xilinx's XCV1000E version. Developed and implemented the dynamical linecard, modem bandwidth allocation and sharing. Implemented 4-level QoS ATM traffic shaping, policing functions in euthanasia 512 modem schedulers. Implemented traffic congestion control based on modem and Othello, Shakespeare Essay subport backpressure signals. Euthanasia Oregon. Wrote the new version of the ASIC/FPGA design specification, verification and euthanasia oregon test plan. Developed chip architecture, partitioned, coded in Verilog at watsons theory RTL, fixed bugs for all functions. Wrote model driver and testbench in Verilog and Vera to simulate each new block and euthanasia oregon top level.

Synthesized the ASIC by DC, FPGA by Michelangelo's Essay Synplify with constraints and Tcl script files. Used Synopsys 's DC and PT timing analysis for timing debug and timing closure. Oregon. Wrote test script for still, VxWorks dshell and euthanasia oregon VisionICE to test traffic in iron curtain lab by Adtech, Smartbit. Note: I was awarded Vermax's Gold Pride Award due to dedication to the scheduler chip in 2000. VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April. ATM Simulator FPGA Design Utilizing PCI Bus. VHDL, Synopsys DC, PT, VerilogXL, Viewlogic, Xilinx, C++, PCI32, Logic Analyzer, Scope. Developed an ASIC/FPGA chip for a low cost, high performance ATM simulator to help in the research and oregon teaching of ATM networks in real world in cooperation of EE and CS departments.

Successfully developed, implemented and tested the ATM chip in the XC4062XLA-09. Developed basic system functions, specifications and architecture for the ATM Simulator. Defined functions of the ATM cell monitor, capture, drop, delay, insertion, error generation. Euthanasia. Created a VHDL design flow, partitioned the chip, and coded in VHDL at RTL. Designed an EDIF netlist core based PCI32 backend application interface in VHDL. Wrote model drivers, testbench in VHDL, then simulated each block and top level. Synthesized by Synopsys's Design Compiler. Timing debug and closure by Primetime. Lab test by summary C++ programs developed to test functions on a PCI32 FPGA prototyping board.

VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April. Some Course Projects in VLSI and Real-time OS. Verilog, Vera, Specman, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. CMOS devices and IC analog circuits design and robinson essay analysis using Cadence Analog Work Bench. CMOS IC digital circuits from RTL to layout using Synopsys and euthanasia oregon Cadence IC tools. Verilog calculator design synthesized by Synopsys and implementation in Xilinx FPGA. VHDL tutorial: Traffic light system synthesized and simulated by Mentor Quick HDL. Co-supervised senior thesis: RISC design and implementation in Xilinx's FPGA.

Real-time, multitasking programming in C using various semaphores for QNX real-time OS. Diamond Graphics Inc, Ontario, Canada. 1996 Sept - 1997 Aug. Hardware Engineer, FPGA Designer. (Permanent full-time) Development of MCU-based Controller for a graphic scanner. Synplify, Xilinx FPGA, OrCAD Schematic and PCB, PC DOS and MCU programming in robinson C. Developed a MCU-based high-accuracy digital controller for euthanasia, a graphic scanner. Developed a new digital control algorithm for a high-accuracy stepper motor. Designed a MCU-based prototyping board to demo the new control algorithm. FPGA design in curtain significance Xilinx F1.5, and board schematic and PCB design in OrCAD. PC DOS programming and MCU 8051 firmware programming in C.

Digital Design Center, Wuhan, China. 1994 Sept - 1996 June. Ph.D. Euthanasia Oregon. Project. Computer-based Non-contact Microsurface Online Measurement. Math algorithms and hardware implementation, DSP, Matlab, OrCAD, MCU 8098 and C firmware. Took part of Fresco The Last Judgment Essay, a team to develop a Computer Integrated Manufacture System (CIMS). Othello, Shakespeare. Developing fast and precise online algorithms based on microscope and CCD sensors.

Developed a MCU-base prototyping board to demo a new fast and precise online algorithm. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug. Lead Hardware Engineer, System Engineer. Euthanasia. (Permanent full-time) Computer-based Data Acquisition Network System Development. PC-based Application System design, Digital and Analog Board design, MCU Firmware in robinson essay C. Developing a specific Remote Data Acquisition and euthanasia oregon Processing System for customers.

Leaded a team to successfully develop some computer-based data acquisition network systems, typically which have over 1000 points and summary of macbeth act 2 are over 100Km away from host control room. Euthanasia. Successfully developed some MCU-based electronic measure instruments for robinson essay, these projects. Designed system scheme, circuit boards and firmware in C and euthanasia debugged in labs. Supports. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug.

Hardware Engineer, Firmware Programmer. Is Jeffrey Dahmer. (Permanent full-time) An electronic teaching laboratory Development. Schematic and PCB design in euthanasia oregon Protel, GAL, PAL, 8051 and firmware in robinson C, DOS programming in C. Developing an electronic system to be used for teaching spoken English. Leaded a team to design, test and install the oregon electronic teaching laboratory for summary of macbeth act 2, customers. Designed a PC-based host to control an audio network comprised of all 64 audio terminals. Designed a digital encoder-based mixed-signal circuit board for the 64 audio terminals.

Department of Computer Engineering, Wuhan University, China. Developed a Laser-based 2D Intelligent Automatic Measure Coordinator. HeNi Laser device and modulation, stepper motor control, photo-electron sensor, H/W and S/W. Design a transmitter with Laser and euthanasia a receiver with a coordinator to measure physical displacements. Successfully developed a MPU-controlled automatic measure coordinator with stepper motors.

Utilized a modulated Laser beam; Used 8031 MCU to be a controller and programmed in C. Training Courses at Nortel Networks from 2000 to 2001. Advanced DC Synthesis Workshop. Oregon. Synopsys's VERA HVL Workshop High-level Chip Design in Verilog. Verification Strategies in theory of caring Verilog High-Speed Circuit Design. Primetime Training Workshop PowerPC 8260 Workshop.

Tornado Training Workshop. Master Degree Courses (1997-1999 in EE and CS ) GPA = 87% ( 4.0 / 4.3 ) EE6123 Semiconductor Devices ( CMOS Modeling ) EE4173 Devices and circuits for VLSI ( CMOS IC processing ) EE6133 VLSI Circuits Design ( analog VLSI circuits ) EE6213 ASIC Design ( digital ASIC design ) CS6812 Computer Aided Logic Design ( logic methodology ) CS6845 Computer Networks and Open Systems ( IP Networks ) EE4243 Data Communications ( Modem, Ethernet ) EE4273 Real Time Operation of Microcomputers (RT Programming ) EE6373 Signal Processor Architecture EE4543 DSP II ( digital filter design ) CS4815 Advanced Computer Architecture CS5865 Data Networks II.